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參數(shù)資料
| 型號(hào)： | SAE81C91 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 20/41頁 |
| 文件大?。?/td> | 521K |
| 代理商： | SAE81C91 |
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07Feb95@09:05h Intermediate Version
Semiconductor Group
26
SAE 81C90/91
Transmit Request Registers
The Transmit Request Set Registers provide a transmission request bit (TRSn) for each message
object. Setting a transmission request bit causes the respective message x to be transmitted. The
bit is cleared by hardware after transmission. Several bits can be set simultaneously. In this way all
messages whose request bits are set are transmitted in turn, starting with the memory location with
the highest number.
Note: A transmission request bit is set by writing ’1’ to the respective bit location (TRSn). Writing ’0’
has no effect.
n = 0...15
The Transmit Request Reset Registers provide a transmit request reset bit (TRRn) for each
transmit request bit TRSn, i.e. for each message object.
Writing ’1’ to a TRRn bit clears the corresponding transmission request bit TRSn. This causes a
transmission request, initiated by the corresponding bit TRSn, to be cancelled, provided that it is not
currently processed.
This scheme avoids conflicts when writing to register bits while they are cleared by hardware
because of a completed transmission.
Note: Registers TRRRx cannot be read.
TRSR2
76543210
Address: 09H
TRS15
TRS14
TRS13
TRS12
TRS11
TRS10
TRS9
TRS8
Reset Value: 00H
rw
TRSR1
76543210
Address: 08H
TRS7
TRS6
TRS5
TRS4
TRS3
TRS2
TRS1
TRS0
Reset Value: 00H
rw
Bit(field)
Function
TRSn
Transmit Request Set Bit
’0’:
No change of the respective transmit request bit.
’1’:
The respective transmit request bit is cleared.
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