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參數(shù)資料
| 型號： | SAE81C91 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 521K |
| 代理商： | SAE81C91 |
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07Feb95@09:05h Intermediate Version
Semiconductor Group
25
SAE 81C90/91
Receive-Ready Registers
These register bits can be reset by writing ’0’ to the respective bit, writing ’1’ has no effect. Bit RRn
is set when a message has arrived and been written into the memory location of message n. Setting
this bit by hardware can generate a receive interrupt, which can be blocked by bit RIMn in the
receive-interrupt-mask register.
Bits RRn must be reset by software.
Receive-Interrupt-Mask Registers
Setting bit RIMn enables a receive interrupt to be generated if the receive-ready bit RRn has been
set, i.e. a message has arrived and was written into the memory location of message n.
Note: Bit ERI in the interrupt-mask register IM blocks all receive interrupts, even if bits RIMn are
set.
RRR2
76543210
Address: 05H
RR15
RR14
RR13
RR12
RR11
RR10
RR9
RR8
Reset Value: 00H
rw
RRR1
76543210
Address: 04H
RR7
RR6
RR5
RR4
RR3
RR2
RR1
RR0
Reset Value: 00H
rw
Bit(field)
Function
RRn
Receive Ready Bit
’0’:
No new message received in object n.
’1’:
A new message has been received and stored in object n.
RIMR2
76543210
Address: 07H
RIM15
RIM14
RIM13
RIM12
RIM11
RIM10
RIM9
RIM8
Reset Value: 00H
rw
RIMR1
76543210
Address: 06H
RIM7
RIM6
RIM5
RIM4
RIM3
RIM2
RIM1
RIM0
Reset Value: 00H
rw
Bit(field)
Function
RIMn
Receive Interrupt Mask Bit
’0’:
No interrupt upon reception of object n.
’1’:
When a new message is stored in object n an interrupt is generated.
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