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參數(shù)資料
| 型號： | SAE81C91 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 17/41頁 |
| 文件大?。?/td> | 521K |
| 代理商： | SAE81C91 |
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07Feb95@09:05h Intermediate Version
Semiconductor Group
23
SAE 81C90/91
Bit-Length Registers
Note: Not defined bit positions must be ’0’ for write accesses.
The Bit Length Registers BL1 and BL2 can only written while bit IM (MOD.0) is set.
1) If the bus lines work according to the ISO specification, additional circuitry is necessary for
interconnection of the input comparator to the bus lines.
BL1
76543210
Address: 00H
SAM
TS2
TS1
Reset Value: 00H
rw
Bit(field)
Function
TS1
Length of Timing Segment 1 (TSeg1).
t
TSeg1 = (TS1 + 1) × tSCL. For tSCL see baud-rate prescaler BRP.
TS2
Length of Timing Segment 2 (TSeg2).
t
TSeg2 = (TS2 + 1) × tSCL. For tSCL see baud-rate prescaler BRP.
SAM
Sample Rate
’0’:
Input signal is sampled once per bit.
’1’:
Input signal is sampled three times per bit.
Note: Bit SAM should only be set to ’1’ using very low baud rates.
BL2
76543210
Address: 01H
IPOL
DI
–
SM
SJW
Reset Value: 00H
rw
-
rw
Bit(field)
Function
SJW
Maximum Synchronization Jump Width.
t
SJWidth = (SJW + 1) × tSCL. For tSCL see baud-rate prescaler BRP.
SM
Speed Mode (Defines edge used for synchronization)
’0’:
Recessive to dominant is used.
’1’:
Both edges are used.
Note: According to the CAN specification this bit should not be set to ’1’.
DI
Digital Input
’0’:
The input signal is applied to the input comparator. 1)
’1’:
The input signal on pin RX0 is evaluated digitally.
The input comparator is inactive. Pin RX1 should be on
V
SS.
IPOL
Input Polarity
’0’:
The input level remains unaltered.
’1’:
The input level is inverted.
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