
q
High Performance 16-bit CPU with 4-Stage Pipeline
q
80 ns Instruction Cycle Time at 25-MHz CPU Clock
q
400 ns Multiplication (16
× 16 bits), 800 ns Division (32 / 16 bit)
q
Enhanced Boolean Bit Manipulation Facilities
q
Additional Instructions to Support HLL and Operating Systems
q
Register-Based Design with Multiple Variable Register Banks
q
Single-Cycle Context Switching Support
q
Clock Generation via on-chip PLL or via direct or prescaled clock input
q
Up to 16 MBytes Linear Address Space for Code and Data
q
1 KByte On-Chip Internal RAM (IRAM)
q
128 KByte On-Chip Flash EPROM with 0 Waitstate Operation
q
5 V Flash Programming Voltage
q
Minimum 1000 Program/Erase Cycles
q
Minimum 10 Years Data Retention
q
Programmable External Bus Characteristics for Different Address Ranges
q
8-Bit or 16-Bit External Data Bus
q
Multiplexed or Demultiplexed External Address/Data Buses
q
Five Programmable Chip-Select Signals (Latched/Unlatched)
q
Hold- and Hold-Acknowledge Bus Arbitration Support
q
1024 Bytes On-Chip Special Function Register Area
q
Idle and Power Down Modes
q
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
q
16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns
q
Two Multi-Functional General Purpose Timer Units with 5 Timers
q
Two Serial Channels (Synchronous/Asynchronous and Synchronous)
q
Programmable Watchdog Timer
q
Oscillator Watchdog
q
Up to 77 General Purpose I/O Lines
q
Boot Support Mechanism
q
Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards
q
100-Pin TQFP Package (Thin QFP)
This document describes the SAB-C163-16FF and the SAB-C163-16F25F.
For simplicity all versions are referred to by the term C163-16F throughout this document.
C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers
Preliminary
C163-16F
16-Bit Microcontroller
C163-16F
Semiconductor Group
3
1997-10-01