參數(shù)資料
型號(hào): SAB-C163-16F25F
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: METRIC, PLASTIC, TQFP-100
文件頁(yè)數(shù): 17/66頁(yè)
文件大?。?/td> 669K
代理商: SAB-C163-16F25F
1997 Intermediate Version
Semiconductor Group
24
1997-10-01
C163-16F
Flash Operating Modes
For the operation of the on-chip Flash module basically three operating modes can be
distinguished:
In Standard Read Mode the Flash memory appears like a standard ROM allowing all code and
data accesses in any addressing mode without waitstates. Standard read mode is entered:
q
after the deactivation of CPU reset (max. 100 s after reset state is finished)
q
after a successful erase operation
q
after a successful programming operation
q
when a command sequence error is detected
q
after a “reset to read” command
Note: Standard read mode is indicated by status bit BUSY=’0’.
In Burst Mode a programming operation is prepared by writing to the Flash assembly buffer. Burst
mode begins after the “Enter Burst Mode” command sequence and ends after the “Store Burst”
command sequence. Burst mode allows the assembly (writing) of 32 words (=64 bytes) at standard
CPU speed, which are the programmed in a single self-timed programming cycle.
Burst mode is only left after the “Store Burst” command sequence, if the buffer was filled with exactly
32 words. If more or less than 32 words have been written the “Store Burst” command will not be
executed and a burst error is indicated instead (BUER=’1’).
Note: During burst mode standard read accesses can still be executed. However, the code to fill
the buffer must be executed from locations outside the Flash memory (e.g. RAM or external
memory).
In Command Mode the C163-16F executes a Flash command (erase sector, program buffer, reset
state machine, etc.) which has been defined by a previous command sequence. During command
mode (indicated by bit BUSY=’1’) no other Flash operations/accesses are possible except for
reading the Flash status.
General rules for command sequences:
q
code must be executed from locations outside the Flash memory
q
all addresses must point into the active Flash space
q
only register-indirect addressing is possible
q
pauses between command cycles are allowed
Note: Carefully check the addresses used during command sequences. When using DPPs or EXT
instructions the resulting address must be within the active Flash space. For the special
addresses (see table below) bits A15...A1 are regarded. A sector address must point to the
first (lowest) location within the target sector.
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