參數(shù)資料
型號: SAA7705H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Car radio Digital Signal Processor(DSP)(車載電臺數(shù)字信號處理器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
文件頁數(shù): 36/60頁
文件大?。?/td> 1857K
代理商: SAA7705H
1999 Aug 16
36
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
12.2
I
2
C-bus protocol
12.2.1
A
DDRESSING
Before any data is transmitted on the I
2
C-bus, the device
that should respond is addressed first. The addressing is
alwaysdonewiththefirstbytetransmittedaftertheSTART
procedure.
12.2.2
S
LAVE ADDRESS
The SAA7705H acts as a slave receiver or a slave
transmitter. Therefore, the clock signal SCL is only an
input signal. The data signal SDA is a bidirectional line.
The slave address is shown in Table 3.
Table 3
Slave address
The sub-address bit A0 corresponds to the hardware
address pin A0 which allows the device to have 2 different
addresses. The A0 input is also used in the test mode as
a serial input of the test control block.
12.2.3
W
RITE CYCLES
The I
2
C-bus configuration for a write cycle is shown in
Fig.17. The write cycle is used to write the bytes to control
the DCS block, the PLL for the DSP clock generation, the
IAC settings, the AD volume control settings, the analog
input selection, the format of the I
2
S-bus and some other
settings. More details can be found in the I
2
C-bus memory
map (see Table 5).
Thedatalengthis2 or 3 bytesdependingontheaccessed
memory. If the Y-memory is addressed the data length is
2 bytes, in case of the X-memory the length is 3 bytes.
The slave receiver detects the address and adjusts the
number of bytes accordingly.
12.2.4
R
EAD CYCLES
The I
2
C-bus configuration for a read cycle is shown in
Fig.18. The read cycle is used to read the data values from
XRAM or YRAM. The master starts with a START
condition (S), the DSP address ‘0011100’ and a logic 0
(write) for the read/write bit. This is followed by an
acknowledge of the SAA7705H. Then the master writes
the high memory address (ADDR H) and low memory
address (ADDR L) where the reading of the memory
content of the SAA7705H must start. The SAA7705H
acknowledges these addresses both.
The master generates a repeated START and again the
SAA7705H address ‘0011100’ but this time followed by a
logic 1 (read) of the read/write bit. From this moment on
the SAA7705H will send the memory content in groups of
2 (Y-memory) or 3 (X-memory) bytes to the I
2
C-bus, each
time acknowledged by the master. The master stops this
cycle by generating a negative acknowledge, then the
SAA7705H frees the I
2
C-bus and the master can generate
a STOP condition.
The data is transferred from the DSP register to the
I
2
C-bus register at execution of the MPI instruction in the
DSP program. Therefore at least once every DSP cycle an
MPI instruction should be added.
MSB
LSB
0
0
1
1
1
0
A0
R/W
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SAA7706H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car radio Digital Signal Processor (DSP)
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SAA7706H/N107,518 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIRAC-1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
SAA7706H/N107,557 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
SAA7706H/N107S,518 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC CAR RADIO DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT