參數(shù)資料
型號(hào)： SAA7705H
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Car radio Digital Signal Processor（DSP）(車(chē)載電臺(tái)數(shù)字信號(hào)處理器)
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
文件頁(yè)數(shù)： 11/60頁(yè)
文件大?。?/td> 1857K
代理商： SAA7705H
1999 Aug 16
11
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
8
FUNCTIONAL DESCRIPTION
The SAA7705H consists of a DSP core and periphery.
The DSP core is described in Sections 8.6, 8.7 and 8.11.
The periphery handles the following tasks:
FM and level information processing (see Section 8.1)
Analog source selection and analog-to-digital
conversion of the analog audio sources (see
Section 8.2)
Digital-to-analog conversion of the DSP output QDAC
(see Section 8.3)
Clock circuit and oscillator (see Section 8.4)
Equalizer accelerator circuit (see Section 8.5)
I
2
C-bus interface (see Section 8.8 and Chapter 12)
RDS decoder (see Section 8.10).
8.1
FM and level information processing
8.1.1
S
IGNAL PATH FOR LEVEL INFORMATION
For FM weak signal processing and for AM and FM
purposes (absolute level and multipath), an FM level and
an AM level input is implemented (pins FML and AML).
In the case of radio reception clocking of the filters and the
level-ADC is based on a 38 kHz sample frequency.
The DC input signal is converted by a bitstream first-order
Sigma-Delta ADC followed by a decimation filter.
The input signal has to be obtained from the radio part.
Two different configurations for AM and FM reception are
possible:
Acircuitwithtwoseparatelevelsignals:oneforFM level
and one for AM level
A combined circuit with AM and FM level information on
the FM level input.
The level input is selected with bit LEVAM-FM of the SEL
register (see Table 12 and Chapter 12).
8.1.2
S
IGNAL PATH FROM
FMMPX
INPUT TO
IAC
AND
STEREO DECODER
The SAA7705H has four analog audio source channels.
One of the analog inputs is the FM multiplex signal.
Selection of this signal can be achieved by the SEL
register bits AUX-FM and CD-TAPE (see Table 12).
The multiplexed FM signal is converted to the digital
domain in SCAD1, a bitstream third-order SCAD. The first
decimation with a factor of 16 takes place in down sample
filter ADF1. This decimation filter can be switched by
means of the SEL register bit WIDE-NARROW
(see Table 12)in thewideor narrowbandposition. Incase
of FM reception, it must be in the narrow position.
The FMMPX path is followed by the sample-and-hold
switch of the IAC (see Section 8.1.5) and the 19 kHz pilot
signal regeneration circuit. A second decimation filter
reduces the output of the IAC to a lower sample rate.
One of the two filter outputs contains the multiplexed
signal with a frequency range of 0 to 60 kHz.
The outputs of this signal path to the DSP (which are all
running on a sample frequency of 38 kHz) are:
Pilot presence indication: Pilot-I. This one bit signal is
LOW for a pilot frequency deviation <4 kHz and HIGH
for a pilot frequency deviation >4 kHz and locked on a
pilot tone.
FM reception stereo signal. This is the 18-bit output of
the stereo decoder after the matrix decoding in
Information System Network (ISN) I
2
S-bus format.
This signal is fed via a multiplexer to a general I
2
S-bus
interface block that communicates with the DSP core.
A noise level indication. This signal is derived from the
first MPX decimation filter via a wide band noise filter.
Detection is done with an envelope detector. This noise
level is filtered in the DSP core and is used to optimize
the FM weak signal processing.
8.1.3
I
NPUT SENSITIVITY FOR
FM
AND
RDS
SIGNALS
The FM and RDS input sensitivity is designed for tuner
front ends which deliver an output voltage varying from
65 to 225 mV (RMS) at a sweep of 22.5 kHz for a 1 kHz
tone. The intermediate standard input sensitivities can be
reached in steps of 1.6 dB, to be programmed with the
AD register bits VOLFM and VOLRDS (see Tables 9
and 17). The volume control of the FMMPX and the
FMRDS input can be controlled separately. VOLFM and
VOLRDS = 000isthemostsensitiveposition,VOLFMand
VOLRDS = 111 the least sensitive position. Due to the
analog circuit control of the volume gain, the input
impedanceofpin FMMPXorpin FMRDSchangeswiththe
volume setting.
8.1.4
AD
INPUT SELECTION SWITCH
Pin SELFR makes it possible to change to another
transmitter frequency with the same radio program to
assess the quality of that signal. In case of a stronger
transmitter signal the decision can be made by the
software to switch to the new transmitter. The FMMPX
input is normally used to process the FM signal.
This FMMPX input is connected via a relative large
capacitor to the MPX tuner output. Switching the tuner to
another transmitter frequency means another DC voltage
level on the MPX output of the tuner and a charging of the
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7706H 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Car radio Digital Signal Processor (DSP)
SAA7706H/N107 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
SAA7706H/N107,518 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DIRAC-1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
SAA7706H/N107,557 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC DIGITAL SIGNAL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
SAA7706H/N107S,518 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC CAR RADIO DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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