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參數(shù)資料
| 型號： | SAA7705H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Car radio Digital Signal Processor（DSP）(車載電臺數(shù)字信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大小： | 1857K |
| 代理商： | SAA7705H |
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1999 Aug 16
19
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (DSP)
SAA7705H
Table 2
Equalizer port list
NAME
DESCRIPTION
Data to/from DSP core
IN FL
IN FR
IN RL
IN RR
OUT FL
OUT FR
OUT RL
OUT RR
Front Left input bus, 18 bits
Front Right input bus, 18 bits
Rear Left input bus, 18 bits
Rear Right input bus, 18 bits
Front Left output bus, 18 bits
Front Right output bus, 18 bits
Rear Left output bus, 18 bits
Rear Right output bus, 18 bits
From EQ register
TWO-FOUR
two or four channel configuration
switch, I
2
C-bus controlled; see Table 9
Control from DSP
clk
CORE
start
DSP core clock, at least 480f
s
new sample start pulse, input and
output registers written
new coefficient word available
new coefficient word loaded in
coefficient memory
address for new coefficient word, 6 bits,
range is from 0 to 39
new coefficient word, 16 bits
data-valid
acknowledge
new-address
new-coefword
In Table 2 the port pinning is depicted. This equalizer
accelerator circuit (EQ) can make a two-channel equalizer
of 10 second-order sections per channel or a four-channel
equalizer of 5 second-order sections per channel
depending on the value of AD register bit TWO-FOUR
(see Table 9). It takes an input sample set of 2 (stereo)
samples or 4 (stereo front and rear) samples via 4 input
registers. It delivers an output sample set of 2 or
4 samples via 4 output registers. All input and output
registers are 18 bits wide.
A pulse of three clock cycles long of the signal start based
on the word select of the used signal path refreshes the
EQ input and output registers and starts up the EQ
controller.
This sequence is shown in Fig.8.
8.5.3
C
ONTROLLER AND PROGRAMMING CIRCUIT
A controller is used to generate the bit control and
word control signals for the filter section data path, the
addresses for the coefficient memory and the control
signals for the input and output selections and
conversions. Depending on the AD register
bit TWO-FOUR (see Table 9), control signals for a two- or
four-channel equalizer are generated.
The 40 coefficient words should be addressed via
40 registers (addresses 0F80H to 0FA7H).
The new coefficient word rate must be slower than 0.5f
s
,
e.g. 22 kHz. The equalizer is programmed by dedicated
software.
Fig.8 Derivation of the gated clock from clk
CORE
.
handbook, full pagewidth
MGM128
audio sample period
480 clkCORE cycles
gated clock
start
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7706H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Car radio Digital Signal Processor (DSP) |
| SAA7706H/N107 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107,518 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIRAC-1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107,557 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107S,518 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC CAR RADIO DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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