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參數(shù)資料
| 型號(hào)： | SAA7184 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital Video Encoders DENC2-M6 |
| 中文描述： | 數(shù)字視頻編碼器DENC2 - M6的 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 180K |
| 代理商： | SAA7184 |
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1996 Jul 03
7
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
FUNCTIONAL DESCRIPTION
The digital MPEG-compatible video encoder (DENC2-M6)
encodes digital luminance and chrominance into analog
CVBS and S-Video (Y/C) signals simultaneously. NTSC-M
and PAL B/G standards and sub-standards are also
supported.
The basic encoder function consists of subcarrier
generation and colour modulation plus insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of RS-170-A and CCIR 624.
For ease of analog post filtering the signals are twice
oversampled, with respect to the pixel clock, before
digital-to-analog conversion.
For total filter transfer characteristics see Figs 3, 4,
5 and 6. The DACs are realized with full 10-bit resolution.
The encoder provides three 8-bit wide data ports that
serve different applications.
The MPEG port and the video port accept 8 lines
multiplexed Cb-Y-Cr data.
The video port is also able to accommodate DIG-TV2
family compatible 16-bit YUV signals. In this event, the
data port is used for the U/V components.
Alternatively, the data port can accommodate the data of
an 8-bit wide microprocessor interface.
The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656
(D1 format) compatible, but the SAV, EAV etc. codes are
not decoded.
A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock frequency of
13.5 MHz, needs to be supplied externally. A crystal
oscillator input/output pair of pins and an on-chip clock
driver are provided optionally. It is also possible to connect
the Philips Digital Video Decoder (SAA7111 or
SAA7151B) in conjunction with a CREF clock qualifier to
the DENC2-M6 via the RETCI pin (connected to RTCO) of
a decoder. Information concerning the actual subcarrier,
PAL-ID and (with SAA7111) definite subcarrier phase can
be inserted.
The DENC2-M6 synthesizes all necessary internal
signals, colour subcarrier frequency and synchronization
signals, from that clock. The DENC2-M6 is always the
timing master for the MPEG port but can also be
configured as master or slave for the video port.
The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with Macrovision.
It also supports OVL via KEY and 3-bit overlay techniques
using a 24
×
8 LUT.
The IC can be programmed via the I
2
C-bus or via the 8-bit
MPU interface, but only one interface configuration can be
active at a time. If the 16-bit video port mode (VP and DP)
is being used, only the I
2
C-bus interface can be selected.
A number of possibilities are provided for setting the
different video parameters such as:
black and blanking level control
colour subcarrier frequency
black variable burst amplitude etc.
During reset (RES = LOW) and after reset is released, all
digital I/O stages are set to the input mode. A reset forces
the control interfaces to abort any running bus transfer and
to set register 3AH to contents 1FH, register 61H to
contents 06H, and registers 6CH and 7AH to contents
00H. All other control registers are not influenced by a
reset.
Data manager
Real time arbitration on the data stream to be encoded is
performed in the data manager.
Depending on the hardware conditions (signals on pins
SEL_ED, KEY, OVL2 to OVL0, MP7 to MP0, VP7 to VP0
and DP7 to DP0) and different software programming,
either data from the MP port, from the VP port or from the
OVL port, is selected to be encoded to CVBS and Y/C
signals.
Optionally, the OVL colour look-up tables located in this
block can be read out in a pre-defined sequence
(8 steps per active video line) thereby achieving, for
example, a colour bar test pattern generator without the
need for an external data source. The colour bar function
is only under software control.
Encoder
V
IDEO PATH
The encoder generates luminance and colour subcarrier
output signals, suitable for use as CVBS or separate Y/C
signals, from the Y, U and V baseband signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7187 | Digital video encoder (DENC2-SQ)(數(shù)字視頻編碼器) |
| SAA7188A | Digital Video Encoder (DENC2-M)(數(shù)字視頻編碼器(DENC2-M)) |
| SAA7201 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7201H | Integrated MPEG2 AVG decoder |
| SAA7212 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7184WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoders DENC2-M6 |
| SAA7185 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2 |
| SAA7185B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoders DENC2-M6 |
| SAA7185BWP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoders DENC2-M6 |
| SAA7185WP | 制造商:NXP Semiconductors 功能描述: 制造商:Philips Semiconductor 功能描述: |
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