1996 Jul 03
4
Philips Semiconductors
Preliminary specification
Digital Video Encoders (DENC2-M6)
SAA7184; SAA7185B
PINNING
SYMBOL
PIN
I/O
I/O
DESCRIPTION
V
SSD1
DP4 to DP7
1
digital ground 1
Upper 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of
the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the
video port are used.
Raster control 1 for video port; depending on the synchronization mode, this
pin receives or provides a VS/FS/FSEQ signal.
Raster control 2 for video port; depending on the synchronization mode, this
pin receives or provides an HS/HREF/CBL signal.
digital ground 2
Video port; this is an input for CCIR 656 compatible multiplexed video data. If
the 16-bit DIG-TV2 format is used, then Y data is input.
digital supply voltage 1
select encoder data; selects input data either from the MPEG port or from
the video port
digital ground 3
MPEG port; it is an input for CCIR 656 style multiplexed YUV data.
digital ground 4
Raster control 1 for MPEG port; this pin provides a VS/FS/FSEQ signal.
Raster control 2 for MPEG port; this pin provides an HS pulse for the MPEG
decoder.
key signal for OVL (active HIGH)
on-screen display data; this is the index for the internal OVL look-up tables
digital ground 5
Clock direction; if the CDIR input is HIGH, the circuit receives a clock signal,
if not LLC and CREF are generated by the internal crystal oscillator.
digital supply voltage 2
Line-locked clock; this is the 27 MHz master clock for the encoder. The
direction is set by the CDIR pin.
Clock reference signal; this is the clock qualifier for DIG-TV2 compatible
signals. The polarity is programmable by software.
crystal oscillator output (to crystal)
Crystal oscillator input (from crystal). If the oscillator is not used, this pin
should be connected to ground.
digital ground 6
Real time control Input; if the clock is provided by the SAA7151B or
SAA7111, RTCI should be connected to the RTCO pin of the decoder to
improve the signal quality.
test pin (should be connected to digital ground for normal operation)
test pin (should be connected to digital ground for normal operation)
lower reference voltage input for the DACs
upper reference voltage input for the DACs
analog positive supply voltage 1 for the DACs and output amplifiers
2 to 5
RCV1
6
I/O
RCV2
7
I/O
V
SSD2
VP0 to VP7
8
I
9 to 16
V
DDD1
SEL_ED
17
18
I
I
V
SSD3
MP7 to MP0
V
SSD4
RCM1
RCM2
19
I
O
O
20 to 27
28
29
30
KEY
OVL0 to OVL2
V
SSD5
CDIR
31
I
I
I
32 to 34
35
36
V
DDD2
LLC
37
38
I
I/O
CREF
39
I/O
XTALO
XTALI
40
41
O
I
V
SSD6
RTCI
42
43
I
AP
SP
V
refL
V
refH
V
DDA1
44
45
46
47
48
I
I
I