- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385813 > SAA2022 (NXP Semiconductors N.V.) Tape formatting and error correction for the DCC system PDF資料下載
參數(shù)資料
| 型號： | SAA2022 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Tape formatting and error correction for the DCC system |
| 中文描述： | 磁帶格式和糾錯的數(shù)控系統(tǒng) |
| 文件頁數(shù)： | 31/52頁 |
| 文件大小： | 208K |
| 代理商： | SAA2022 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
February 1994
31
PORTAB
Portable application active HIGH, allows for the data
channels clock extraction to track fast variations in tape bit
rate. For home use set to inactive.
NOCOS
No Corrected Output Symbol active HIGH, disables the
writing of the error corrected output to the DRAM. It is only
used for debugging.
TEST2
This setting is for test only. For use in applications this bit
should always be programmed to logic 0.
PINO2
Pin output 2, Port expander output for the microcontroller.
PINO3
Pin output 3, Port expander output for the microcontroller.
T
APE
P
HASE
M
ODE
ENFREG = logic 0, ENEFREG = logic 0 and
μ
CSPD = logic 0
In this mode the SAA2022 performs a new calculation to
determine the pulse width for the SPEED signal
approximately once every 21.33 ms, giving a sampling
rate of approximately 46.9 Hz. This calculation is basically
a phase comparison between the incoming main data tape
frame and an internally generated reference. The pulse
duty cycle increases linearly from approximately 9% when
the incoming main data tape frame is 1.65 tape blocks
(8.8 ms) too early up to 91% when the incoming main data
tape frame is 1.65 tape blocks (8.8 ms) too late, in 256
steps (see Fig.20). Outside
±
2 tape blocks range the pulse
width characteristic overflows and repeats itself forming a
saw-tooth pattern. The SAA2022 has an internal buffer of
±
8.8 ms inside which the phase information is valid.
T
APE
F
REQUENCY
M
ODE
ENFREG = logic 1, ENEFREG = logic 0 and
μ
CSPD = logic 0
The above description is overridden with frequency
information. That is if the incoming main data bit rate
deviates by more than approximately
±
6% from the
nominal bit rate of 96000 bits per second, frequency
information is mixed with the phase information. In
between the limits
±
6% the pulse width is determined as
above.
E
XTENDED
T
APE
F
REQUENCY
M
ODE
ENFREG = logic 1, ENEFREG = logic 1 and
μ
CSPD = logic 0
In this mode there are 3 regions. This provides a more
gentle transition from frequency plus phase control to
phase only control. Firstly from 0% to
±
4.5% deviation,
where the operation is as for the tape phase mode.
Secondly from
±
4.5% to
±
6% deviation where the
contribution of the frequency information to the servo
information is half of that in the region beyond
±
6%
deviation. Thirdly when the deviation is greater than
±
6%,
which is the same as for the tape frequency mode.
M
ICROCONTROLLER
M
ODE
μ
CSPD = logic 1
In this mode the pulse width is determined by the
microcontroller programming of the SPDDTY interface
register.
NMODE0, NMODE1
These two bits control the mode change operation in the
SAA2022.
Table 5
NMODE1, NMODE0.
NMODE1
NMODE0
OPERATING MODE
0
0
DPAP
1
0
DPAR
1
1
DRAR
0
1
invalid state
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA2022GP | Tape formatting and error correction for the DCC system |
| SAA4995WP | Panorama-IC (PAN-IC)(全景畫面IC) |
| SAA55XX | TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) |
| SAA6712E | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| SAA6713AH | XGA analog input flat panel controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2022GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Tape formatting and error correction for the DCC system |
| SAA2023 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems |
| SAA2023GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems |
| SAA2023H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems |
| SAA2032 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital equalization for the tape drive processing of the DCC system |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。