參數(shù)資料
型號(hào)： SAA2022
廠商： NXP Semiconductors N.V.
英文描述： Tape formatting and error correction for the DCC system
中文描述： 磁帶格式和糾錯(cuò)的數(shù)控系統(tǒng)
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 208K
代理商： SAA2022
February 1994
17
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
Fig.11 DRAM timing read cycle.
MEA702
MCLK
RASN
CASN
D0...D3
A0...A7 (A8)
OEN
WEN
1 read cycle = 651 ns
ROW
COLUMN #0
COLUMN #1
COLUMN #2
#1
#2
#0
DRAM Interface
The SAA2022 has been designed to operate with
64 k
×
4-bit or 256 k
×
4-bit DRAMs operating in page
mode, with an access time of 80 to 100 ns. The timing for
read, write and refresh cycles is shown in Figs 11 to 13.
CASN
This output pin is the column address strobe (active LOW)
for the DRAM, it connects directly to the column address
strobe pin of the DRAM.
RASN
This output pin is the row address strobe (active LOW) for
the DRAM, it connects directly to the row address strobe
pin of the DRAM.
OEN
This pin provides the output enable (active LOW) for the
DRAM, it connects directly to the output enable pin of the
DRAM.
WEN
This output pin provides the write enable (active LOW) for
the DRAM, it connects directly to the write enable pin of the
DRAM.
A0
TO
A8
These output pins are the multiplexed column and row
address lines for the DRAM. When the 64 k
×
4-bit DRAM
is used, pins A0 to A7 should be connected to the DRAM
address input pins, and pin A8 should be left unconnected.
When using the 256 k
×
4-bit DRAM then address pins
A0 to A8 should be connected to the address input pins of
the DRAM.
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SAA2022GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Tape formatting and error correction for the DCC system
SAA2023 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems
SAA2023GP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems
SAA2023H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Drive processor for DCC systems
SAA2032 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital equalization for the tape drive processing of the DCC system
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