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參數(shù)資料
| 型號： | SAA2022 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Tape formatting and error correction for the DCC system |
| 中文描述： | 磁帶格式和糾錯的數(shù)控系統(tǒng) |
| 文件頁數(shù)： | 15/52頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SAA2022 |
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Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
February 1994
15
SBMCLK
This is the sub-band master clock input for the
SB-I
2
S-interface. The frequency of this signal is nominally
6.144 MHz. This pin should be connected to the SBMCLK
pin of the SAA2002.
SBDIR
This output pin is the sub-band I
2
S-bus direction signal, it
indicates the direction of transfer on the SB-I
2
S-bus.
A logic 1 indicates a SAA2022 to SAA2002 transfer
(audio play) whilst a logic 0 is output for a SAA2002 to
SAA2022 transfer (audio record). This pin connects
directly to the SBDIR pin on the SAA2002.
SBCL
This input/output pin is the bit clock line for the
SB-I
2
S-interface to the SAA2002. Is has a nominal
frequency of 768 kHz.
SBWS
This input/output pin is the word select line for the
SB-I
2
S-interface to the SAA2002. It has a nominal
frequency of 12 kHz.
SBDA
This input/output pin is the serial data line for the
SB-I
2
S-interface to the SAA2002.
SBEF
This active HIGH output pin is the error per byte line for the
SB-I
2
S-interface to the SAA2002.
URDA
This active HIGH output pin indicates that the main data
(audio), the SYSINFO and the AUXILIARY data are
not
usable, regardless of the state of the corresponding
reliability flags. The state of this pin is reflected in the
URDA bit of STATUS byte 0, which can be read by the
microcontroller. This pin should be connected directly to
the URDA pin of the SAA2002. URDA is activated as a
result of a reset, a mode change from DRAR to DPAP, or
if the SAA2022 has had to resynchronize with the incoming
data from tape.
The position of the first SB-I
2
S-bytes in a tape frame is
shown in Fig.10.
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