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參數(shù)資料
| 型號(hào)： | SAA2022 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Tape formatting and error correction for the DCC system |
| 中文描述： | 磁帶格式和糾錯(cuò)的數(shù)控系統(tǒng) |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SAA2022 |
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February 1994
18
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
MEA703
MCLK
RASN
CASN
D0...D3
A0...A7 (A8)
OEN
WEN
1 write cycle = 651 ns
ROW
COLUMN #0
COLUMN #1
COLUMN #2
#1
#2
#0
Fig.12 DRAM write cycle.
D0
TO
D3
These input/output pins are the data lines for the DRAM,
they should be connected directly to the DRAM data I/O
pins.
Write amplifier interface
The SAA2022 may be used with either the TDA1316 or
TDA1319 write amplifiers.
WCLOCK
This output pin provides the 3.072 MHz clock output for the
WRITE AMPLIFIER, it should be connected directly to the
WCLOCK pin of the WRITE AMPLIFIER.
WDATA
This output pin is the multiplexed data and control line for
the WRITE AMPLIFIER (timing information is shown in
Fig.14). The WDATA pin should be connected directly to
the WDATA pin of the WRITE AMPLIFIER.
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