參數(shù)資料
型號: S3F49FAXZA
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP100
封裝: 14 X 14 MM, TQFP-100
文件頁數(shù): 7/27頁
文件大?。?/td> 282K
代理商: S3F49FAXZA
SPECIFICATION
S3F49FAX
14
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
100-Pin Number
I/O
Description
XINPACK
79
O
INPUT PORT ACKNOWLEDGE:
This signal is not used in memory mode. The Input
acknowledge signal is asserted by the PC Card when the card
is selected and responding to an I/O read cycle at the address
that is on the address bus.
This signal is used by the host to control the enable of any
input data buffers between the PC Card and the CPU.
In True IDE mode, this output signal is not used and should be
connected at the host.
XRDY
88
O
READY/BUSY:
In memory mode, this signal is set high when the PC Card is
ready to accept a new data transfer operation and held low
when the card is busy. The host memory card socket must
provide a pull-up resistor. At power up and at reset, the RDY/-
BSY signal is held low (busy) until the PC Card has completed
its power up or reset function.
No access of any type should be made to the PC Card during
this time. The RDY/-BSY signal is held high (disabled from
being busy) whenever the following condition is true:
The PC Card has been powered up with +RESET continuously
disconnected or asserted.
I/O operation - After the PC Card has been configured for I/O
operation, this signal is used as Interrupt request. This line is
strobed low to generate a pulse mode interrupt or held low for
a level mode interrupt.
In True IDE mode, this signal is the active high Interrupt
request to the host.
XIORD
95
I
I/O READ:
This signal is not used in memory mode.This is an I/O read
strobe generated by the host. This signal gates I/O data onto
the bus from the PC Card when the card is configured to use
the I/O interface.
In True IDE Mode, this signal has the same function as in PC
Card I/O Mode.
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