參數(shù)資料
型號: S3F49FAXZA
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP100
封裝: 14 X 14 MM, TQFP-100
文件頁數(shù): 6/27頁
文件大?。?/td> 282K
代理商: S3F49FAXZA
SPECIFICATION
S3F49FAX
13
Table 3. Signal Description for PCMCIA/IDE Interface (Continued)
Signal Name
100-Pin Number
I/O
Description
XWE
90
I
WRITE ENABLE:
This is a signal driven by the host and used for strobing memory
write data to the registers of the PC Card when the card is
configured in the memory interface mode. It is also used for
writing the configuration registers.
In PC Card I/O mode, this signal is used for writing the
configuration registers. In True IDE mode, this input signal is not
used and should be connected to VCC by the host.
XWAIT
81
O
WAIT:
The -WAIT signal is driven low by the PC Card to signal the host
to delay completion of a memory or I/O cycle that is in progress.
IORDY:
In True IDE mode, this output signal may be used as IORDY.
XWP/
XIOIS16
66
O
I/O PORT IS 16 BITS:
Memory mode - The PC Card does not have a write protect
switch. This signal is held low after the completion of the reset
initialization sequence.
I/O operation - When the PC Card is configured for I/O operation
pin 24 is used for the -I/O selected is 16-Bit Port (-IOIS16)
function. A low signal indicates that a 16 bit or odd byte only
operation can be performed at the addressed port.
In True IDE mode, this output signal is asserted low when this
device is expecting a word data transfer cycle.
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