參數(shù)資料
型號: S3F49FAXZA
元件分類: 存儲控制器/管理單元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PQFP100
封裝: 14 X 14 MM, TQFP-100
文件頁數(shù): 4/27頁
文件大?。?/td> 282K
代理商: S3F49FAXZA
SPECIFICATION
S3F49FAX
11
2.3 Signal descriptions
Table 3. Signal Description for PCMCIA/IDE Interface
Signal Name
100-Pin Number
I/O
Description
XA0
74
XA1
78
XA2
80
XA3
82
XA4
84
XA5
85
XA6
87
XA7
89
XA8
91
XA9
93
XA10
97
I
ADDRESS BUS[10:0]:
These address lines along with the –REG signal
are used to select the following:
The I/O port address registers within the PC
Storage Card, the memory mapped port address
registers within the PC Storage Card, a byte in
the Card's information structure and its
configuration control and status registers.
This signal is the same as the PC Card Memory
Mode signal in PC Card I/O mode.
In True IDE Mode only A[2:0] are used to select
the one of eight registers in the Task File, the
remaining address lines should be grounded by
the host.
XD0
72
XD1
70
XD2
68
XD3
9
XD4
7
XD5
5
XD6
3
XD7
1
XD8
69
XD9
67
XD10
65
XD11
8
XD12
6
XD13
4
XD14
2
XD15
100
I/O
DATA BUS[15:0]:
These lines carry the Data, Commands and
Status information between the host and the
controller. XDB0 is the LSB of the even byte of
the word. XDB8 is the LSB of the odd byte of the
word.
This signal is the same as the PC Card memory
mode signal in PC Card I/O mode.
In True IDE mode, all Task File operations occur
in byte mode on the low order bus XDB0-XDB7
while all data transfers are 16 bit using XDB0-
XDB15
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