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參數(shù)資料
| 型號： | S29AL032D90TFI043 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 32 Megabit CMOS 3.0 Volt-only Flash Memory |
| 中文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | LEAD FREE, MO-142DD, TSOP-48 |
| 文件頁數(shù)： | 37/67頁 |
| 文件大?。?/td> | 1708K |
| 代理商： | S29AL032D90TFI043 |
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S29AL032D
S29AL032D_00_A8 November 2, 2006
Da ta
Sh e e t
12. Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 12.1 on page 44 and the following subsections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
12.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.
This is analogous to the complement/true datum output described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The
system must provide an address within any of the sectors selected for erasure to read valid status information
on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 17.8 on page 54, Data# Polling Timings
(During Embedded Algorithms), under AC Characteristics on page 49 illustrates this.
Figure 12.1 on page 44 shows the outputs for Data# Polling on DQ7. Figure 12.2 on page 43 shows the
Data# Polling algorithm.
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