參數(shù)資料
型號: S25FL064A0LNAI00
廠商: SPANSION LLC
元件分類: PROM
英文描述: 64M X 1 FLASH 3V PROM, PDSO16
封裝: 0.300 INCH, PLASTIC, MS-013AA, SOP-16
文件頁數(shù): 17/36頁
文件大?。?/td> 1495K
代理商: S25FL064A0LNAI00
June 29, 2007 S25FL064A_00_C3
S25FL064A
25
Data
She e t
9.10
Bulk Erase (BE)
The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command
is required prior to writing the PP command.
The host system must drive CS# low, and then write the BE command on SI. CS# must be driven low for the
entire duration of the BE sequence. The command sequence is shown in Figure 9.10 and Table 9.4
The host system must drive CS# high after the device has latched the 8th bit of the CE command, otherwise
the device does not execute the command. The BE operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tBE. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the BE operation is in progress. The WIP
bit is 1 during the BE operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device only executes a BE command if all Block Protect bits (BP2:BP0) are 0 (see Table 7.1
on page 13). Otherwise, the device ignores the command.
Figure 9.10 Bulk Erase (BE) Command Sequence
01
2
4
5
6
7
Command
CS#
SCK
SI
3
SO
Hi-Z
Mode 0
Mode 3
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