參數(shù)資料
型號(hào): S1C88832F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP128
封裝: PLASTIC, QFP-128
文件頁數(shù): 75/160頁
文件大小: 1244K
代理商: S1C88832F0A0100
S1C88832/88862 TECHNICAL MANUAL
EPSON
13
3 CPU AND MEMORY CONFIGURATION
3 CPU AND MEMORY CONFIGURATION
In this section, we will explain the CPU and memory configuration.
3.1 CPU
The S1C88832/88862 utilize the S1C88 8-bit core
CPU whose resistor configuration, command set,
etc. are virtually identical to other units in the
family of processors incorporating the S1C88.
See the "S1C88 Core CPU Manual" for the S1C88.
The S1C88832/88862 supports Model 3/minimum
mode of the S1C88 CPU which allows accessing of
the internal memory mapped within the physical
space from 000000H to 00FFFFH.
3.2 Internal Memory
The S1C88832/88862 is equipped with internal
ROM and RAM as shown in Figure 3.2.1.
3.2.1 ROM
The internal ROM capacity is shown in Table
3.2.1.1.
Table 3.2.1.1 Internal ROM capacity
Fig. 3.2.1 Internal memory map
I/O memory
Display memory
Unused area
RAM
(1.5K bytes)
ROM
(60K bytes)
S1C88832
S1C88862
00FFFFH
00FF00H
00FD42H
00F800H
00F7FFH
00F600H
00F5FFH
00F000H
00EFFFH
008000H
007FFFH
000000H
I/O memory
Display memory
Unused area
RAM
(1.5K bytes)
Unused area
ROM
(32K bytes)
Model
S1C88832
S1C88862
ROM capacity
32K bytes
60K bytes
Address
000000H–007FFFH
000000H–00EFFFH
3.2.2 RAM
The internal ROM capacity is shown in Table
3.2.2.1.
Table 3.2.2.1 Internal ROM capacity
Model
S1C88832
S1C88862
RAM capacity
1.5K bytes
Address
00F000H–00F5FFH
3.2.3 I/O memory
A memory mapped I/O method is employed in the
S1C88832/88862 for interfacing with internal
peripheral circuit. Peripheral circuit control bits and
data register are arranged in data memory space.
Control and data exchange are conducted via
normal memory access. The I/O memory is
arranged from address 00FF00H to address
00FFFFH. See Section 5.1, "I/O Memory Map", for
details of the I/O memory.
3.2.4 Display memory
The S1C88832/88862 is equipped with an internal
display memory which stores a display data for
LCD driver.
The display memory is arranged from address
00F800H to address 00FD42H (including the
unused area). See Section 5.11, "LCD Controller",
for details of the display memory.
3.3 Exception Processing Vectors
Address 000000H to address 000023H in the
program area of the S1C88832/88862 is assigned as
exception processing vectors. Furthermore, from
address 000026H to address 0000FFH, software
interrupt vectors are assignable to any two bytes
which begin with an even address.
Table 3.3.1 lists the vector addresses and the
exception processing factors to which they
correspond.
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