參數(shù)資料
型號(hào): S1C88832F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP128
封裝: PLASTIC, QFP-128
文件頁(yè)數(shù): 21/160頁(yè)
文件大?。?/td> 1244K
代理商: S1C88832F0A0100
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S1C88832/88862 TECHNICAL MANUAL
EPSON
109
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
5.13 Supply Voltage Detection
(SVD) Circuit
5.13.1 Configuration of SVD circuit
The S1C88832/88862 has a built-in supply voltage
detection (SVD) circuit configured with a 4-bit
successive approximation A/D converter.
The SVD circuit has 16 sampling levels (level 0–
level 15) for supply voltage, and this can be control-
led by software.
In addition, an initial reset signal can be generated
when the supply voltage drops to level 0 or less.
This is selected by the mask option.
Figure 5.13.1.1 shows the configuration of the SVD
circuit.
5.13.2 Operation of SVD circuit
s Sampling control of the SVD circuit
The SVD circuit has two operation modes: continu-
ous sampling and 1/4 Hz auto-sampling mode.
Operation mode selection is done by the SVD control
registers SVDON and SVDSP as shown in Table
5.13.2.1. When both bits of SVDON and SVDSP are
set to "1", continuous sampling is selected.
Table 5.13.2.1 Correspondence between control register
and operation mode
In both operation modes, reading SVDON can
confirm whether the SVD circuit is operating
(BUSY) or on standby (READY); "1" indicates BUSY
and "0" indicates READY.
When executing an SLP instruction while the SVD
circuit is operating, the stop operation of the OSC1
oscillation circuit is kept waiting until the sampling
is completed. The two bits of SVDON and SVDSP
are automatically reset to "0" by hardware while
waiting for completion of sampling.
To reduce current consumption, turn the SVD
circuit OFF when it is not necessary.
s Detection result
The SVD circuit A/D converts the supply voltage
(VDD–VSS) by 4-bit resolution and sets the result
thereof into the SVD0–SVD3 register.
The data in SVD0–SVD3 correspond to the detec-
tion levels as shown in Table 5.13.2.2 and the
detection data is maintained until the next sam-
pling.
For the correspondence between the detection level
and the supply voltage, see "7 ELECTRICAL
CHARACTERISTICS".
An interval of 7.8 msec (fOSC1 = 32.768 kHz) is
required from the start of supply voltage sampling
by the SVD circuit to completion by writing the
result into SVD0–SVD3. Therefore, when reading
SVD0–SVD3 before sampling is finished, the
previous result will be read.
Fig. 5.13.1.1 Configuration of SVD circuit
VDD
Data
bus
SVD3
SVD2
SVD1
SVD0
2,048 Hz
Sampling
control
circuit
SVDON
SVDSP
Mask option
fOSC1 Dividing
circuit
OSC1
oscillation
circuit
Reference voltage
generation circuit
Internal initial reset
Other reset factor
Initial
reset
circuit
1/4 Hz
4-bit A/D
converter
SVDON
0
1
Operating mode
SVD circuit OFF
1/4 Hz auto-sampling ON
Continuous sampling ON
SVDSP
0
1
×
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