
I-112
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
PSC00, PSC01: 00FF31HD3, D4
PSC10, PSC11: 00FF32HD3, D4
Select the dividing ratio of the prescaler.
Two-bit PSC00 and PSC01 is the prescaler dividing
ratio selection registers for timer 0, and the two-bit
PSC10 and PSC11 correspond to timer 1. The
prescaler dividing ratios that can be set by these
registers are shown in Table 5.11.10.2.
Table 5.11.10.2 Selection of prescaler dividing ratio
In event counter mode
When "1" is written: With noise rejecter
When "0" is written: Without noise rejecter
Reading:
Valid
In the event counter mode, select whether the noise
rejecter for the K10 input port terminal will be
selected or not.
When "1" is written to FCSEL, the noise rejecter is
selected and counting is done by an external clock
(EVIN) with 0.98 msec or more pulse width. (The
noise rejecter allows clocking counter at the second
falling edge of the internal 2,048 Hz signal after
changing the input level of the K10 input port
terminal. Consequently, the pulse width that can
reliably be rejected is 0.48 msec.)
When "0" is written to FCSEL, the noise rejector is
not selected and the counting is done directly by an
external clock (EVIN) input to the K10 input port
terminal.
At initial reset, FCSEL is set to "0".
PLPOL: 00FF31HD5
Selects the pulse polarity for the K10 input port
terminal.
In event counter mode
When "1" is written: Rising edge
When "0" is written: Falling edge
Reading:
Valid
In the event counter mode, select whether the count
timing will be set at the falling edge of the external
clock (EVIN) input to the K10 input port terminal
or at the rising edge. When "0" is written to PLPOL,
the falling edge is selected and when "1" is written,
the rising edge is selected.
In pulse width measurement mode
When "1" is written: HIGH level pulse width
measurement
When "0" is written: LOW level pulse width
measurement
Reading:
Valid
In the pulse width measurement mode, select
whether the LOW level width of the signal (EVIN)
input to the K10 input port terminal will be meas-
ured or the HIGH level will be measured. When "0"
is written to PLPOL, the LOW level width measure-
ment is selected and when "1" is written, the HIGH
level width measurement is selected.
In the normal mode (EVCNT = FCSEL = "0"), the
setting of PLPOL becomes invalid.
At initial reset, PLPOL is set to "0".
When event counter mode has been selected, the
setting of the PSC00 and PSC01 becomes invalid. In
the same way, the PSC10 and PSC11 setting be-
comes invalid when 16-bit mode has been selected.
At initial reset, this register is set to "0" (input clock/1).
EVCNT: 00FF31HD7
Selects the counter mode for the timer 0.
When "1" is written: Event counter mode
When "0" is written: Timer mode
Reading:
Valid
Select whether timer 0 will be used as an event
counter or a timer. When "1" is written to EVCNT,
the event counter mode is selected and when "0" is
written, the timer mode is selected.
At initial reset, EVCNT is set to "0" (timer mode).
FCSEL: 00FF31HD6
Selects the function for each counter mode of timer 0.
In timer mode
When "1" is written: Pulse width measurement
timer mode
When "0" is written: Normal mode
Reading:
Valid
In the timer mode, select whether timer 0 will be
used as a pulse width measurement timer or a
normal timer. When "1" is written to FCSEL, the
pulse width measurement mode is selected and the
counting is done according to the level of the signal
(EVIN) input to the K10 input port terminal. When
"0" is written to FCSEL, the normal mode is selected
and the counting is not affected by the K10 input
port terminal.
PSC11
PSC01
PSC10
PSC00
Prescaler dividing ratio
1
0
1
0
1
0
Input clock / 64
Input clock / 16
Input clock / 4
Input clock / 1