
I-32
EPSON
S1C88348/317/316/308 TECHNICAL HARDWARE
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(c) I/O Memory map (00FF10H–00FF13H)
Address Bit
Name
00FF10 D7
D6
D5
D4
D3
D2
D1
D0
–
LCCLK
LCFRM
DTFNT
LDUTY
SGOUT
SR R/W
Function
Comment
–
CL output control for expanded LCD driver
FR output control for expanded LCD driver
LCD dot font selection
LCD drive duty selection
R/W register
Constantry "0" when
being read
10
–
0
R/W
–
On
5 x 5 dots
1/16 duty
1
–
Off
5 x 8 dots
1/32 duty
0
00FF11 D7
D6
D5
D4
D3
D2
D1
D0
–
DSPAR
LCDC1
LCDC0
LC3
LC2
LC1
LC0
–
LCD display memory area selection
LCD display control
LCD contrast adjustment
"0" when being read
These bits are reset
to (0, 0) when
SLP instruction
is executed.
–
0
R/W
–
Display area 1
–
Display area 0
LCDC1
1
0
LCDC0
1
0
1
0
LCD display
All LCDs lit
All LCDs out
Normal display
Drive off
LC3
1
:
0
LC2
1
:
0
LC1
1
:
0
LC0
1
0
:
0
Contrast
Dark
:
Light
*1
Reserved register
00FF12 D7
D6
D5
D4
D3
D2
D1
D0
–
SVDSP
SVDON
SVD3
SVD2
SVD1
SVD0
–
SVD auto-sampling control
SVD continuous sampling control/status
SVD detection level
Constantry "0" when
being read
These registers are
reset to "0" when
SLP instruction
is executed.
*3
–
0
1
→0*2
0
X
R/W
R
–
On
Busy
On
–
Off
Ready
Off
R
W
SVD3
1
:
0
SVD2
1
:
0
SVD1
1
:
0
SVD0
1
0
:
0
Detection level
Level 15
Level 14
:
Level 0
*1 When 1/8 duty has been selected by mask option, setting of this register becomes invalid.
*2 After initial reset, this status is set "1" until conclusion of hardware first sampling.
*3 Initial values are set according to the supply voltage detected at first sampling by hardware.
Until conclusion of first sampling, SVD0–SVD3 data are undefined.
00FF13 D7
D6
D5
D4
D3
D2
D1
D0
–
CMP1ON
CMP0ON
CMP1DT
CMP0DT
–
Comparator 1 On/Off control
Comparator 0 On/Off control
Comparator 1 data
Comparator 0 data
Constantly "0" when
being read
–
0
R/W
R
–
On
+ > -
–
Off
+ < -