參數(shù)資料
型號(hào): S1C88308D0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, UUC170
封裝: DIE-170
文件頁(yè)數(shù): 277/343頁(yè)
文件大小: 2396K
代理商: S1C88308D0A0100
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S1C88348/317/316/308 TECHNICAL HARDWARE
EPSON
I-27
4 INITIAL RESET
4.1.1 RESET terminal
Initial reset can be done by executed externally
inputting a LOW level to the RESET terminal.
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset.
In addition, be sure to use the RESET terminal for
the first initial reset after the power is turned on.
The RESET terminal is equipped with a pull-up
resistor. You can select whether or not to use by
mask option.
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is to
input a LOW level simultaneously to the input ports
(K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port terminal
at LOW level for two seconds (when the oscillation
frequency is fOSC1 = 32.768 kHz) or more to
perform the initial reset by means of this function.
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
(1) Not use
(2) K00 & K01
(3) K00 & K01 & K02
(4) K00 & K01 & K02 & K03
For instance, let's say that mask option (4) "K00 &
K01 & K02 & K03" is selected.
When the input level at input ports K00–K03 is
simultaneously LOW, initial reset will take place.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
4.1.3 Supply voltage detection (SVD) circuit
When the SVD circuit detects that supply voltage
has dropped below level 0 four successive times
(see Chapter 7, "ELECTRICAL CHARACTERIS-
TICS"), it outputs an initial reset signal until the
supply voltage has been restored to level 2.
You can select whether or not to use the initial reset
according to the SVD circuit by mask option. If you
use it, the supply voltage must be at least level 2 for
the first sampling of the SVD circuit, when the
power is turned on. At this time, if the power
voltage level is less than level 2, the initial reset
status will not be canceled and instead the SVD
circuit will continue sampling until the supply
voltage reaches level 2 or more.
For more information, see "5.15 Supply Voltage
Detection (SVD) Circuit" in this Manual.
4.1.4 Initial reset sequence
After cancellation of the LOW level input to the
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscillation
stabilization waiting time (8,192/fOSC1 sec.) has
elapsed. When the initial reset by the SVD circuit
has been used, an initial sampling time (248/fOSC1
sec.) is added as additional waiting time.
Figure 4.1.4.1 shows the operating sequence
following initial reset release.
PC
00-0000
Dummy
VECL
fOSC1
RESET
Internal initial reset
Internal address bus
Internal data bus
Internal read signal
8192/fOSC1 [sec]
Oscillation stable waiting time
248/fOSC1 [sec]
First SVD sampling time *
Dummy cycle
Reset exception processing
*
When the initial reset by the SVD circuit with the mask option has been used, this cycle is inserted as the waiting time.
Fig. 4.1.4.1 Initial reset sequence
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