- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25640 > S1C7XXXF00E199 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP PDF資料下載
參數(shù)資料
| 型號： | S1C7XXXF00E199 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP |
| 文件頁數(shù)： | 150/196頁 |
| 文件大小： | 1650K |
| 代理商： | S1C7XXXF00E199 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁當(dāng)前第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁
6 FUNCTIONS
S1C17 FAMILY S1C17 CORE MANUAL
EPSON
6-7
6.3.2 Vector Table
Vector table in the S1C17 Core
The table below lists the interrupts for which the vector table is referenced during interrupt handling.
Table 6.3.2.1 Vector List
Interrupt
Reset
Address misaligned interrupt
NMI
Maskable external interrupt 3
:
Maskable external interrupt 31
Vector No.
Software interrupt No.
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
:
31 (0x1f)
Vector address
TTBR + 0x00
TTBR + 0x04
TTBR + 0x08
TTBR + 0x0c
:
TTBR + 0x7c
The vector address is one that contains a vector (or the jump address) for the user’s interrupt handler routine
that is provided for each interrupt and is executed when the relevant interrupt occurs. Because an address value
is stored, each vector address is located at a 16-bit boundary. The memory area in which these vectors are
stored is referred to as the “vector table.” The “TTBR” in the Vector Address column represents the base (start)
address of the vector table. For the TTBR value, refer to the Technical Manual of each model. The set value can
be read from TTBR (trap table base register) located at address 0xffff80.
6.3.3 Interrupt Handling
When an interrupt occurs, the processor starts interrupt handling. (This interrupt handling does not apply for reset
and debug interrupts.)
The interrupt handling performed by the processor is outlined below.
(1) Suspends the instructions currently being executed.
An interrupt is generated synchronously with the rising edge of the system clock at the end of the cycle of the
currently executed instruction.
(2) Saves the contents of the PC and PSR to the stack (SP), in that order.
(3) Clears the IE (interrupt enable) bit in the PSR to disable maskable interrupts that would occur thereafter. If
the generated interrupt is a maskable interrupt, the IL (interrupt level) in the PSR is rewritten to that of the
generated interrupt.
(4) Reads the vector for the generated interrupt from the vector table, and sets it in the PC. The processor thereby
branches to the user’s interrupt handler routine.
After branching to the user’s interrupt handler routine, when the reti instruction is executed at the end of interrupt
handling, the saved data is restored from the stack in order of the PC and PSR, and the processing returns to the
suspended instructions.
6.3.4 Reset
The processor is reset by applying a low-level pulse to its rst_n pin. All the registers are thereby cleared to 0.
The processor starts operating at the rising edge of the reset pulse to perform a reset sequence. In this reset
sequence, the reset vector is read out from the top of the vector table and set in the PC. The processor thereby
branches to the user’s initialization routine, in which it starts executing the program. The reset sequence has priority
over all other processing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2041 | PHOTO TRANSISTOR DETECTOR |
| S3P44R10 | TRIGGER OUTPUT SOLID STATE RELAY, 4000 V ISOLATION-MAX |
| S3S12P128J0VQK | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, PQFP80 |
| MC9S12P128J0CFTR | 16-BIT, FLASH, 1.05 MHz, MICROCONTROLLER, QCC48 |
| MC3S12P128J0VFTR | 16-BIT, MROM, 1.05 MHz, MICROCONTROLLER, QCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C88349 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88650 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88655 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88816 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。