
APPENDIX
LIST
OF
S
1C
17
CORE
INSTR
UCTIONS
Ap-6
EPSON
S1C17
F
AMIL
Y
S1C17
CORE
MANU
AL
Branch Instructions
S1C17 Core Instruction Set
Opcode
jpr / jpr.d
jpa / jpa.d
jrgt / jrgt.d
jrge / jrge.d
jrlt / jrlt.d
jrle / jrle.d
jrugt / jrugt.d
jruge / jruge.d
jrult / jrult.d
jrule / jrule.d
jreq / jreq.d
jrne / jrne.d
call / call.d
calla / calla.d
ret / ret.d
int
intl
reti / reti.d
brk
retd
Operand
sign10
%rb
imm7
%rb
sign7
sign10
%rb
imm7
%rb
imm5
imm5, imm3
Function
pc
←pc+2+sign11; sign11={sign10,0} (3)
pc
←pc+2+rb (3)
pc
←imm7 (3)
pc
←rb (3)
pc
←pc+2+sign8 if !Z&!(N^V) is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if !(N^V) is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if N^V is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if Z | (N^V) is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if !Z&!C is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if !C is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if C is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if Z | C is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if Z is true; sign8={sign7,0} (3)
pc
←pc+2+sign8 if !Z is true; sign8={sign7,0} (3)
sp
←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+sign11; sign11={sign10,0} (3)
sp
←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+rb (3)
sp
←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←imm7 (3)
sp
←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←rb (3)
pc
←A[sp](23:0), sp←sp+4 (3)
sp
←sp-4, A[sp]←{psr, pc+2}, pc←vector(TTBR+imm5×4)
sp
←sp-4, A[sp]←{psr, pc+2}, pc←vector(TTBR+imm5×4), psr(IL)←imm3
{psr, pc}
←A[sp], sp←sp+4
A[DBRAM]
←{psr, pc+2}, A[DBRAM+4]←r0, pc←0xfffc00
r0
←A[DBRAM+4](23:0), {psr, pc}←A[DBRAM]
Cycle
3
2(.d)
3
2(.d)
2
(false)
or
3
(true)
5
2(.d)
4
3(.d)
4
3(.d)
3, 2(.d)
3
3, 2(.d)
4
EXT
4
–
2
–
1
4
–
2
–
D
–
0
1
0
1
0
1
0
1
0
1
0
1
0
d
0
1
0
1
d
0
1
0
1
0
IL
–
–
IE
–
0
0
Z
–
–
N
–
–
C
–
–
V
–
–
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
d
0
d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Code
MSB
LSB
Mnemonic
Flags
Remarks
1) With one EXT: displacement = sign21 (= {imm13, sign7, 0}), With two EXT: displacement = sign24 (= {1st imm13(2:0), 2nd imm13, sign7, 0})
2) With one EXT: absolute address= sign20 (= {imm13, imm7}), With two EXT: absolute address = sign24 (= {1st imm13(3:0), 2nd imm13, imm7})
3) These instructions become a delayed branch instruction when the d bit in the code is set to 1 by suffixing ".d" to the opcode (jrgt.d, call.d, etc.).
4) With one EXT: displacement = sign24 (= {imm13, sign10, 0})
5) The conditional branch instructions other than delayed instructions (without ".d") are executed in two cycles when the program flow does not branch or three cycles when the program flow branches.
Immediate Extension Instruction
S1C17 Core Instruction Set
Opcode
ext
Operand
imm13
Function
Extends the immediate or operand of the following instruction.
Cycle
1
EXT
1
D
–
0 1 0
IL
–
IE
–
Z
–
N
–
C
–
V
–
Code
MSB
LSB
Mnemonic
Flags
Remarks
1) One or two ext instruction can be placed prior to the instructions that can be extended.
imm7
sign10
sign7
imm7
imm5
imm3
rb
imm13