
S1C63455 TECHNICAL MANUAL
EPSON
29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.4.4 I/O memory of input ports
Table 4.4.4.1 shows the I/O addresses and the control bits for the input ports.
Table 4.4.4.1 Control bits of input ports
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF20H
SIK03
SIK02
SIK01
SIK00
R/W
SIK03
SIK02
SIK01
SIK00
0
Enable
Disable
K00–K03 interrupt selection register
FF21H
K03
K02
K01
K00
R
K03
K02
K01
K00
– 2
High
Low
K00–K03 input port data
FF22H
KCP03
KCP02
KCP01
KCP00
R/W
KCP03
KCP02
KCP01
KCP00
1
K00–K03 input comparison register
FFE4H
0
EIK0
RR/W
0 3
EIK0
– 2
0
Enable
Mask
Unused
Interrupt mask register (K00–K03)
FFF4H
000
IK0
RR/W
0 3
IK0
– 2
0
(R)
Yes
(W)
Reset
(R)
No
(W)
Invalid
Unused
Interrupt factor flag (K00–K03)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
K00–K03: K0 port input port data (FF21H)
Input data of the input port terminals can be read with these registers.
When "1" is read: High level
When "0" is read: Low level
Writing: Invalid
The reading is "1" when the terminal voltage of the four bits of the input ports (K00–K03) goes high
(VDD), and "0" when the voltage goes low (VSS).
These bits are dedicated for reading, so writing cannot be done.
SIK00–SIK03: K0 port interrupt selection register (FF20H)
Selects the ports to be used for the K00–K03 input interrupts.
When "1" is written: Enable
When "0" is written: Disable
Reading: Valid
Enables the interrupt for the input ports (K00–K03) for which "1" has been written into the interrupt
selection registers (SIK00–SIK03). The input port set for "0" does not affect the interrupt generation
condition.
At initial reset, these registers are set to "0".
KCP00–KCP03: K0 port input comparison register (FF22H)
Interrupt conditions for terminals K00–K03 can be set with these registers.
When "1" is written: Falling edge
When "0" is written: Rising edge
Reading: Valid
The interrupt conditions can be set for the rising or falling edge of input for each of the four bits (K00–
K03), through the input comparison registers (KCP00–KCP03).