參數(shù)資料
型號(hào): S1C63455F
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP128
封裝: PLASTIC, QFP5-128
文件頁數(shù): 45/119頁
文件大?。?/td> 865K
代理商: S1C63455F
S1C63455 TECHNICAL MANUAL
EPSON
23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.3.3 OSC3 oscillation circuit
The S1C63455 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Max. 4 MHz)
for high speed operation and the source clock for peripheral circuits needing a high speed clock (pro-
grammable timer, FOUT output). The mask option enables selection of either the CR or ceramic oscilla-
tion circuit. When CR oscillation is selected, only a resistance is required as an external element. When
ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are
required.
Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.
C CR
OSC3
OSC4
R
CR2
VSS
CGC
CDC
Ceramic
OSC4
OSC3
R
RDC
FC
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
To CPU
(and some peripheral circuits)
Oscillation circuit control signal
(a) CR oscillation circuit
(b) Ceramic oscillation circuit
Fig. 4.3.3.1 OSC3 oscillation circuit
As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR2 between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 7, "Electrical
Characteristics" for resistance value of RCR2.
When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the
ceramic oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3
and OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. For both CGC and CDC,
connect capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit,
oscillation can be stopped by the software (OSCC register).
相關(guān)PDF資料
PDF描述
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