參數(shù)資料
型號: S1C63455F
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP128
封裝: PLASTIC, QFP5-128
文件頁數(shù): 117/119頁
文件大?。?/td> 865K
代理商: S1C63455F
96
Rev. 1.0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA SLICER and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M306H1SFP
UARTi transmit/receive mode register
Symbol
Address
When reset
UiMR(i=0,1)
03A016, 03A816
0016
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
CKDIR
SMD1
SMD0
Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
Parity enable bit
0 : Internal clock
1 : External clock
Stop bit length select bit
Odd/even parity select bit
Sleep select bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits length
1 0 1 : Transfer data 8 bits length
1 1 0 : Transfer data 9 bits length
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
0 : Internal clock
1 : External clock
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Must always be “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
UART2 transmit/receive mode register
Symbol
Address
When reset
U2MR
037816
0016
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : (Note)
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
CKDIR
SMD1
SMD0
Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Usually set to “0”
1 0 0 : Transfer data 7 bits length
1 0 1 : Transfer data 8 bits length
1 1 0 : Transfer data 9 bits length
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
0 : No reverse
1 : Reverse
Usually set to “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Note: Bit 2 to bit 0 are set to “0102” when I
2C mode is used.
Must always be fixed to “0”
Figure 2.11.5 UARTil I/O-related registers (2)
相關(guān)PDF資料
PDF描述
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