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參數資料
| 型號： | RV5C387A |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | I2C-bus Real-Time Clock ICs with Voltage Monitoring Function |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| 封裝： | 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10 |
| 文件頁數： | 33/42頁 |
| 文件大小： | 363K |
| 代理商： | RV5C387A |
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PRELIMINARY RV5C387A
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14.4.2.
Periodic Interrupt
Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two
waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of
around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the
output is return to High (OFF).
Description
Interrupt Cycle and Falling Timing
OFF(H)
Fixed at “L”
2Hz(Duty50%)
1Hz(Duty50%)
Once per 1 second (Synchronized with
Second counter increment)
Once per 1 minute (at 00 seconds of every
Minute)
Once per hour (at 00 minutes and 00
Seconds of every hour)
Once per month (at 00 hours, 00 minutes,
and 00 seconds of first day of every month)
CT2
CT1
CT0
Wave form mode
-
-
Pulse Mode *1)
Pulse Mode *1)
Level Mode *2)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
(Default)
1
0
1
Level Mode *2)
1
1
0
Level Mode *2)
1
1
1
Level Mode *2)
*1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.
In the pulse mode, the increment of the second counter is delayed by approximately 92
μ
s from the falling edge of
clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may appear to lag
behind the time counts of the real-time clocks by approximately 1 second. Rewriting the second counter will
reset the other time counters of less than 1 second, driving the /INTRA pin low.
/INTRA Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
μ
s
(Increment of second counter)
*2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the
falling edge of periodic interrupt signals. For example, periodic interrupt signals with an
interrupt cycle setting of 1 second are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of
±
3.784ms. For
example, 1-Hz clock pulses will have a duty cycle of 50
±
0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of
±
3.784 ms.
/INTRA Pin
(Increment of
second counter)
CTFG Bit
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
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相關代理商/技術參數 |
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