參數(shù)資料
型號: RV5C387A
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: I2C-bus Real-Time Clock ICs with Voltage Monitoring Function
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝: 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10
文件頁數(shù): 10/42頁
文件大小: 363K
代理商: RV5C387A
RV5C387A PRELIMINARY
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13.2.
13.2.1.
Register Settings
Control Register 1 (ADDRESS Eh)
D7
D6
D5
D4
D3
D2
CT2
CT2
0
D1
CT1
CT1
0
D0
CT0
CT0
0
WALE
WALE
0
*) Default settings: Default value means read/written values when the XSTP bit is set to “1” due to power-on
from 0 volts or supply voltage drop.
WALE, DALE
Alarm_W Enable Bit, Alarm_D Enable Bit
WALE,DALE
Description
0
Disabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers).
1
Enabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers)
DALE
DALE
0
/12
24
/12
24
0
/CLEN2
/CLEN2
0
TEST
TEST
0
(For Writing)
(For Reading)
Default Settings *)
(1)
(Default)
(2)
/12
24
12-/24-hour Mode Selection Bit
/12
24
0
Selecting the 12-hour mode with a.m. and p.m. indications.
1
Selecting the 24-hour mode
Setting the /12
24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
Description
(Default)
24-hour mode
12-hour mode
24-hour mode
12-hour mode
00
01
02
03
04
05
06
07
08
09
10
11
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
12
13
14
15
16
17
18
19
20
21
22
23
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
Setting the /12
24 bit should precede writing time data
(3) /CLEN2
32-kHz Clock Output Bit 2
/CLEN2
0
Enabling the 32-kHz clock circuit
1
Disabling the 32-kHz clock circuit
Setting the /CLEN2 bit or the /CLEN1 bit (D3 in the control register 2) to 0 specifies generating clock pulses with
the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely,
setting both the /CELN1 and the /CLEN2 bit to 1 specifies disabling (“H”) such output.
Test Bit
TEST
Description
0
Normal operation mode.
1
Test mode.
The TEST bit is used only for testing in the factory and should normally be set to 0.
Description
(Default)
(4) TEST
(Default)
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