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參數(shù)資料
| 型號： | RV5C387A |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | I2C-bus Real-Time Clock ICs with Voltage Monitoring Function |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| 封裝： | 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10 |
| 文件頁數(shù)： | 32/42頁 |
| 文件大小： | 363K |
| 代理商： | RV5C387A |
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RV5C387A PRELIMINARY
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The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits
in the Control Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and
CT0 bits in the Control Register 1) as listed in the table below.
Flag bits
Enable bits
Output Pin
/INTRB
Alarm_W
WAFG
(D1 at Address Fh)
DAFG
(D0 at Address Fh)
CTFG
(D2 at Address Fh)
WALE
(D7 at Address Eh)
DALE
(D6 at Address Eh)
CT2=CT1=CT0=0
(These bit setting of “0” disable the Periodic Interrupt)
(D2 to D0 at Address Eh)
Alarm_D
/INTRC
Peridic
Interrupt
/INTRA
* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the
/INTRA, /INTRB, and /INTRC pins are driven high (disabled).
14.4.1.
Alarm Interrupt
The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control
Register 1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2). The enable bits can
be used to enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the
flag bits can be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no
event when set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0.
The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm
interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match
between current time and preset alarm time.
The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers
for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour
and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1.
Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon
the coincidental occurrence of a match between current time and preset alarm time in the process of setting
the alarm function.
current time =
preset alarm time
WALE
←
1
(DALE)
WALE
←
0
(DALE)
Interval (1min.) during which a match
between current time and preset alarm time
occurs
current time =
preset alarm time
WAFG
←
0
(DAFG)
Max.61.1
μ
s
/INTRB
(/INTRC)
WALE
←
1
(DALE)
WALE
←
1
(DALE)
current time =
preset alarm time
WALE
←
0
(DALE)
current time =
preset alarm time
/INTRB
(/INTRC)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RV5C387A_03 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION |
| RV5C387AE2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
| RV5C387A-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Real-Time Clock ICs with Voltage Monitoring Function |
| RV5LAYSB102A | 制造商: 功能描述: 制造商:undefined 功能描述: |
| RV5LAYSB254A | 制造商: 功能描述: 制造商:undefined 功能描述: |
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