參數(shù)資料
型號: RF5C62
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: REAL-TIME CLOCK
中文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO18
封裝: SOP-18
文件頁數(shù): 41/48頁
文件大小: 419K
代理商: RF5C62
Category
Questions and Answers
2) Software
Question 4:An attempt to disable an alarm interrupt by setting the ALFG bit to “0” in the control regis-
ter 2 results in holding the INTR pin output low. What is the cause of this phenomenon
Question 3:How can the INTR pin output be used
RP/RF/RS5C62
37
Answer 1:In the typical software-controller process of initialization at power-on from 0V, the BSY bit is set
to “1” in the control register 2 by setting the WTRST bit to “1” in the control register 3 for the
dual purpose of confirming the absence of a carry and confirming the start of oscillation. After
power-on from 0V, the start of oscillation normally requires a time period (oscillation start time)
on the order of 0.1 to 2 seconds, which, in turn, requires additional time to wait for the start of
the crystal oscillators. It seems most likely, therefore, that the BSY bit fails to be switched from
“1” to “0” due to prolonged oscillation start time. Further, another possibility is that the start of
oscillation may be hindered by some trouble (e.g. condensation) with the crystal oscillators. It
is necessary, therefore, to assign a time-out period to exit from the loop for checking the BSY
bit in the control register 2.
Answer 2:As described in “11. 2. 1. Writing to or Reading from Time and Calendar Counters by Stopping
Time Count Operation (by Setting WTEN and BSY Bits)”, the WTEN bit in the control register
1 and the BSY bit in the control register 2 are used to read from the time and calendar counters
in such a manner as to prevent occurrence of an error due to a carry during read operation. If
the BSY bit is found to be “1”, however, this typical software-controlled process involves addi-
tional time to wait for setting of the BSY bit to “0”. To save such wait time, an alternative action
can be taken to read the 1-second digit twice without setting the WTEN and BSY bits as shown
in “11. 2. 3. Reading from Time and Calendar Counters by Dual Reading”. This process fea-
tures dual reading from the 1-second digit in anticipation of an error which may occur due to a
carry during read operation from the time and calendar counters in case of mismatching
between the dual readings.
Answer 3:The INTR pin outputs an alarm interrupt and a cyclic interrupt. For details on these two types of
interrupts, see “5. Interrupts” in “USAGE”.
Answer 4:The INTR pin outputs the logical sum (OR) of an alarm interrupt and a cyclic interrupt when
they are generated in combination. Consequently, an attempt to disable an alarm interrupt by
setting the ALFG bit to “0” may result in holding the INTR pin low when it outputs a cyclic inter-
rupt as well.
Question 1:In the typical software-controlled process of initialization at power-on from 0V, the BSY bit
is checked to find that it fails to be switched from “1” to “0”. What is the cause of this failure
Question 2:How is it possible to read from the time and calendar counters without setting the WTEN
and BSY bits
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