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參數(shù)資料
| 型號： | RF5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO18 |
| 封裝： | SOP-18 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 419K |
| 代理商： | RF5C62 |
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8
RP/RF/RS5C62
2.2 Control Register 2 (BANK0/1 at “Eh”)
D3
*
*
1
D2
D1
D0
BSY
CTFG
ALFG
XSTP
CTFG
ALFG
XSTP
(For write operation)
(For read operation)
XSTP
Function
0
1
Indicates the progress of oscillation. Intended for setting to “0”.
Indicates the stop of oscillation. Not intended for setting to “1”.
ALFG
Function
0
1
Indicates an alarm interrupt is disabled or indicates mismatching between clock
time and alarm time (upon turning off the INTR pin). Intended for setting to “0”.
I
ndicates matching between clock time and alarm time (upon driving low the
INTR pin). Not intended for setting to “0”.
Alarm time match indication bit *
3
CTFG
Function
0
1
Indicates that the INTR pin is turned off. Intended for setting to “0” in the level
mode.
Indicates that the INTR pin is driven low. Not intended for setting to “0”.
Cyclic interrupt indication bit *
4
BSY
Function
0
1
Indicates the normal state of the time and calendar counters (no carry or no
reset pulse).
Indicates the busy state of the time and calendar counters (a carry or a reset
pulse generated).
Time/calendar counter state indication bit *
5
Oscillation stop detection bit *
2
*
1) The BSY bit is intended for only read operation and is not intended for write operation.
*
2) The XSTP bit is used to detect the stop of the crystal oscillator. The XSTP bit is set to “1” upon the stop of oscillation and held at “1” after the restart
of oscillation. Upon detection of the stop of oscillation, the built-in timer counter is reset (because the TM
3
bit in the timer clock selection register is
reset).
*
3) When the ALEN bit is set to “1”, the ALFG bit is also set to “1” upon output of an alarm interrupt from the INTR pin (while it is held low).
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