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參數(shù)資料
| 型號： | RF5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO18 |
| 封裝： | SOP-18 |
| 文件頁數(shù)： | 36/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RF5C62 |
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RP/RF/RS5C62
32
11.2-2 Reading from Time and Calendar Counters by Generating Cyclic Interrupt
YES
NO
Proceed to
interrupt from
other ICs
CTFG=0
Output cyclic interrupt from
INTR pin
*
1
CTFG
0
Read from time and
calendar counters
This typical process of reading from the time and calendar
counters is applied on the conditions below:
1) The INTR pin is set to the level mode (upon setting the CT
3
to “1” in the
interrupt cycle selection register).
2) The route marked with “
*
1” lasts within the time equivalent to a preset
cycle minus 30.5μs (for the purpose of preventing occurrence of an error
due to a carry during reading from the time and calendar counters).
11.2-3 Reading from Time and Calendar Counters by Dual Reading
YES
NO
Dual readings
match
*
1
*
2
Read 1-second digit
Read 1-second digit again
Read from the time and
calendar counters (starting
with address “1h” and
ending with address “Ch”)
*
1) A carry from the second digit starts with 1 second via 10 seconds,---and
1 year, and ends with 10 years. Consequently, reading from the time
and calendar counters must also start with the 10-second digit (at
address “1h” ) and end with the 10-year digit (at address “Ch” ).
*
2) This route assumes that an error occurs due to a carry during reading
from the time and calendar counters.
11.3 Writing Alarm Time to Alarm Registers
Write alarm time
(in minutes and hours)
ALEN
BANK
0
1
ALEN
1
*
1
*
1) Non-existent alarm time may be set in the alarm register, provided that an
alarm interrupt is disabled. To enable an alarm interrupt, existent alarm
time must be set in the alarm register.
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