參數(shù)資料
型號(hào)： RF5C62
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： REAL-TIME CLOCK
中文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO18
封裝： SOP-18
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 419K
代理商： RF5C62
11
RP/RF/RS5C62
2.5 Interrupt Cycle Selection Register (BANK1 at “0h”)
D3
D2
D1
D0
0
0
0
0
CT
3
CT
2
CT
1
CT
0
(For write operation)
(For read operation)
*
1
Interrupt cycle/output mode selection bits *
2
*
1) These bits are intended for only write operation and always read as “0”.
*
2) The CT
3
to CT
0
bits are used to set interrupt cycles and output modes as shown in the table below:
*
) The bits marked with “
*
” are set to “0” or “1”.
CTFG
Preset interrupt cycle
INTR
CTFG
INTR
Interrupt
Setting the CTFG bit to “0”
(Interrupt)
Pulse mode
(The CT
3
bit is set to “0”.)
(The CTFG bit is not intended for write operation.)
Level mode
(The CT
3
bit is set to “1”.)
(The CTFG bit is intended for setting to “0” only.)
CT3
CT2
CT1
CT0
INTR
Remarks
*
*
*
*
*
*
*
*
0
0
0
0
“OFF”
Disable a cyclic interrupt.
0
0
1
2048Hz
Specify a cycle (T) of 0.488ms (1/2048Hz).
0
1
0
1024Hz
Specify a cycle (T) of 0.977ms (1/1024Hz).
0
1
1
128Hz
Specify a cycle (T) of 7.813ms (1/128Hz).
1
0
0
16Hz
Specify a cycle (T) of 62.5ms (1/16Hz).
1
0
1
1Hz
Specify a cycle (T) of 1s (1/1Hz).
1
1
0
1/60Hz
Specify a cycle (T) of 60s (1/1/60Hz).
1
1
1
“ON”
Specify the fixed low level of the INTR pin output.
*
*
*
*
*
*
Pulse mode
Specify a duty cycle of 50%. See below.
1
Level mode
See below.
Relationship between INTR pin output and
upward second count
INTR
INTR
Upward second count
Upward second count
Upward second count
Upward second count
(1) Pulse mode (when 1Hz or 1/60Hz is selected)
(2) Level mode (when 1Hz or 1/60Hz is selected)
30.5μs
30.5μs
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