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參數(shù)資料
| 型號(hào)： | RF5C62 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | REAL-TIME CLOCK |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO18 |
| 封裝： | SOP-18 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 419K |
| 代理商： | RF5C62 |
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18
RP/RF/RS5C62
1.2 Writing Operation
The requirements for writing data to the internal registers and counters are: [1] holding the CE pin high, [2] per-
forming the process of addressing through the A3 to A0 pin inputs, then [3] driving low the CS pin, [4] causing the
WR pin to transition from its high to low to high levels, and thereby [5] causing the D3 to D0 pins to input data to be
written. The writing timing is shown in the chart below.
CE
A0 to A3
D0 to D3
(Write Data)
t
CEH
t
CES
Valid
t
AH(WR)
t
AS(WR)
t
DH
t
DS
or
CS
WR
WR
CS
t
W
[1]
[2]
[3]
[4]
[5]
*
1) The CS and WR pin inputs are interchangeable. The diagonally shaded sections marked in the above timing chart may be set to both high and low
levels. (Consequently, the CS and WR pin inputs may be caused to transition from their high to low levels before the process of addressing.)
*
2) “
t
AS
(WR)” indicates the time required to perform the process of addressing before the start of write operation at which both the WR and CS pin inputs
are driven low.
*
3) “
t
AH
(WR)” indicates the time required to maintain the result of addressing after the completion of write operation at which either the WR or CS pin
input is driven high.
*
) The CE pin must be driven as low as the V
SS
pin whenever possible in order to minimize battery consumption in battery backup (while the CE pin is
held low).
2. Handling of CE Pin
Normally, the CE pin is connected to the supply voltage detection circuit of the system power supply. In switch-
ing the system power supply (see the typical power supply circuit), the CE pin must be driven low before the voltage
across the system power supply drops below the lower limit to the operating voltage of the CPU (at the point ([1])
in the timing chart below) and then driven high after the supply voltage rises above the lower limit to the operating
voltage of the CPU (at the point ([2]) in the timing chart below).
CE
VDD
Lower limit to operating voltage of CPU
Battery voltage
0.2VDD
0.2VDD
MIN.0μs
MIN.0μs
Voltage across system
power supply
[1]
[2]
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