參數(shù)資料
型號(hào)： RD28F6408W30T70
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA80
封裝： 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁(yè)數(shù)： 55/82頁(yè)
文件大小： 749K
代理商： RD28F6408W30T70
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
49
12.2
Flash Write Operations
NOTES:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (t
WLWH
or t
ELEH
) is defined from CE# or WE# low (whichever occurs last) to CE# or
WE# high (whichever occurs first); hence, t
WP
= t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
5. Write pulse width high (t
WHWL
or t
EHEL
) is defined from CE# or WE# high (whichever is first) to CE# or WE#
low (whichever is last). Hence, t
WPH
= t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
.
6. System designers should take this into account and may insert a software No-Op instruction to delay the first
read after issuing a command.
7. For commands other than resume commands.
8. V
PP
should be held at V
PP1
or V
PP2
until block erase or program success is determined.
#
Sym
Parameter
(1,2)
Speed
–
70
–
85
Unit
Note
Min
Max
Min
Max
W1
t
PHWL
(t
PHEL
)
RST# High Recovery to WE# (CE#) Low
150
150
ns
W2
t
ELWL
(t
WLEL
)
CE# (WE#) Setup to WE# (CE#) Low
0
0
ns
W3
t
WLWH
(t
ELEH
)
WE# (CE#) Write Pulse Width Low
4
45
60
ns
W4
t
DVWH
(t
DVEH
)
Data Setup to WE# (CE#) High
45
60
ns
W5
t
AVWH
(t
AVEH
)
Address Setup to WE# (CE#) High
45
60
ns
W6
t
WHEH
(t
EHWH
)
CE# (WE#) Hold from WE# (CE#) High
0
0
ns
W7
t
WHDX
(t
EHDX
)
Data Hold from WE# (CE#) High
0
0
ns
W8
t
WHAX
(t
EHAX
)
Address Hold from WE# (CE#) High
0
0
ns
W9
t
WHWL
(t
EHEL
)
WE# (CE#) Pulse Width High
5, 6, 7
25
25
ns
W10
t
VPWH
(t
VPEH
)
V
PP
Setup to WE# (CE#) High
3
200
200
ns
W11
t
QVVL
V
PP
Hold from Valid Status Register Data
3, 8
0
0
ns
W12
t
QVBL
WP# Hold from Valid Status Register Data
3, 8
0
0
ns
W13
t
BHWH
(t
BHEH
)
WP# Setup to WE# (CE#) High
3
200
200
ns
W14
t
WHGL
(t
EHGL
)
Write Recovery before Read
0
0
ns
W16
t
WHQV
WE# High to Valid Data
6
t
AVQV
+
t
AVQV
+
ns
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