參數(shù)資料
型號： RD28F6408W30B85
廠商： INTEL CORP
元件分類： 存儲器
英文描述： 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA80
封裝： 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁數(shù)： 80/82頁
文件大?。?/td> 749K
代理商： RD28F6408W30B85
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
74
Preliminary
Partition Region 1 Information
(1)
See table below
Address
Len
Bot
2
52:
53:
1
54:
P = 39h
Description
Bottom
(P+19)h
(P+1A)h
(P+1B)h
Top
(P+19)h Number of identical partitions within the partition region
(P+1A)h
(P+1B)h
Simultaneous program and erase operations allowed in other
partitions while a partition in this region is in Read mode
bits 0
–
3 = number of simultaneous Program operations
bits 4
–
7 = number of simultaneous Erase operations
(Optional flash features and commands)
Top
52:
53:
54:
(P+1C)h
(P+1C)h
1
55:
55:
(P+1D)h
(P+1D)h
1
56:
56:
(P+1E)h
(P+1E)h
1
57:
57:
(P+1F)h
(P+20)h
(P+21)h
(P+22)h
(P+23)h
(P+24)h
(P+25)h
(P+1F)h Partition Region 1 Erase Block Region 1 Information
(P+20)h
bits 0
–
15 = y, y+1 = number of identical-size erase blocks
(P+21)h
bits 16
–
31 = z, region erase block(s) size are z x 256 bytes
(P+22)h
(P+23)h Partition 1 (Erase Region 1)
(P+24)h Minimum block erase cycles x 1000
(P+25)h
Partition 1 (erase region 1) bits per cell; internal error correction
bits 0
–
3 = bits per cell in erase region
bit 4 = reserved for
“
internal ECC used
”
(1=yes, 0=no)
bits 5
–
7 = reserve for future use
Partition 1 (erase region 1) page mode and synchronous mode
capabilities defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
4
58:
59:
5A:
5B:
5C:
5D:
5E:
58:
59:
5A:
5B:
5C:
5D:
5E:
2
1
(P+26)h
(P+26)h
1
5F:
5F:
(P+27)h
(P+28)h
(P+29)h
(P+2A)h
(P+2B)h
(P+2C)h
(P+2D)h
Partition Region 1 Erase Block Region 2 Information
bits 0
–
15 = y, y+1 = number of identical-size erase blocks
bits 16
–
31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
Partition 1 (Erase Region 2) minimum block erase cycles x 1000
(bottom parameter device only)
Partition 1 (Erase Region 2) bits per cell
(bottom parameter device only)
bits 0
–
3 = bits per cell in erase region
bit 4 = reserved for
“
internal ECC used
”
(1=yes, 0=no)
bits 5
–
7 = reserve for future use
Partition 1 (Erase Region 2) pagemode and synchronous mode
capabilities defined in Table 10 (bottom parameter device only)
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
4
60:
61:
62:
63:
64:
65:
66:
2
1
(P+2E)h
1
67:
Simultaneous program and erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0
–
3 = number of simultaneous Program operations
bits 4
–
7 = number of simultaneous Erase operations
Simultaneous program and erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0
–
3 = number of simultaneous Program operations
bits 4
–
7 = number of simultaneous Erase operations
Partitions' erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in
“
bulk
”
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
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