參數(shù)資料
型號(hào)： RD28F6408W30B85
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA80
封裝： 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁(yè)數(shù)： 32/82頁(yè)
文件大?。?/td> 749K
代理商： RD28F6408W30B85
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
26
Preliminary
EFP consists of four phases: setup, program, verify and exit. Refer to
Figure 32,
“
Enhanced
Factory Program Flowchart
”
on page 63
for a detailed graphical representation on how to
implement EFP.
5.3.1
EFP Requirements and Considerations
EFP requirements:
Ambient temperature: T
A
= 25
°
C ±5
°
C
V
CC
within specified operating range
V
PP
within specified V
PP2
range
Target block unlocked
EFP considerations:
Block cycling below 10 erase cycles
(1)
RWW not supported
(2)
EFP programs one block at a time
EFP cannot be suspended
(1)
Recommended for optimum performance. Some degradation in performance may occur if this limit is exceeded, but the
internal algorithm will continue to work properly.
(2)
Code or data cannot be read from another partition during EFP.
5.3.2
Setup Phase
After receiving the EFP Setup (30h) and Confirm (D0h) command sequence, device SR.7
transitions from a
‘
1
’
to a
‘
0
’
indicating that the WSM is busy with EFP algorithm startup. A delay
before checking SR.7 is required to allow the WSM time to perform all of its setups and checks
(V
PP
level and block lock status). If an error is detected, status register bits SR.4, SR.3 and/or SR.1
are set and EFP operation terminates.
5.3.3
Program Phase
After setup completion, the host programming system must check SR.0 to determine
“
data-stream
ready
”
status (SR.0=0). Each subsequent write after this is a program-data write to the flash array.
Each cell within the memory word to be programmed to
‘
0
’
will receive one WSM pulse;
additional pulses, if required, occur in the verify phase. SR.0=1 indicates that the WSM is busy
applying the program pulse.
The host programmer must poll the device's status register for the
“
program done
”
state after each
data-stream write. SR.0=0 indicates that the appropriate cell(s) within the accessed memory
location have received their single WSM program pulse, and that the device is now ready for the
next word. Although the host may check full status for errors at any time, it is only necessary on a
block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside the target block
immediately terminates the program phase; the WSM then enters the EFP verify phase.
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