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參數資料
| 型號： | RD28F6408W30B85 |
| 廠商： | INTEL CORP |
| 元件分類： | 存儲器 |
| 英文描述： | 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA80 |
| 封裝： | 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80 |
| 文件頁數： | 23/82頁 |
| 文件大?。?/td> | 749K |
| 代理商： | RD28F6408W30B85 |
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28F6408W30, 28F3204W30, 28F320W30, 28F640W30
Preliminary
17
When CR.10 = 1, WAIT is active high. A
‘
1
’
on the WAIT signal indicates the
“
asserted
”
state.
WAIT signal
“
asserted
”
means that the WAIT signal is indicating a
“
wait
”
condition.
WAIT signal
“
deasserted
”
means that the WAIT signal is NOT indicating a
“
wait
”
condition
(i.e., the bus is valid).
WAIT is High-Z until the device is active (CE# = V
IL
). In synchronous read array mode, when the
device is active (CE# = V
IL
) and data is valid, CR.10 (WT) determines if WAIT goes to V
OH
or
V
OL.
The WAIT signal is only
“
deasserted
”
when data is valid on the bus. Invalid data drives the
WAIT signal to
“
asserted
”
state. In asynchronous page mode, WAIT is always set to an
“
asserted
”
state (CR.10 = 1)
4.2.4
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous burst mode
(CR.15 is set to
“
0
”
), and when addressing a partition that is currently in read array mode. The
WAIT signal is only
“
deasserted
”
when data is valid on the bus. The WAIT signal polarity is set by
CR.10.
When the device is operating in synchronous non-read-array mode, such as read status, read ID, or
read query, WAIT is set to an
“
asserted
”
state as determined by CR.10.
Figure 20 on page 46
displays WAIT Signal in Synchronous Non-Read Array Operation Waveform.
When the device is operating in asynchronous page mode or asynchronous single word read mode,
WAIT is set to an
“
asserted
”
state as determined by CR.10. See
Figure 21,
“
WAIT Signal in
Asynchronous Page-Mode Read Operation Waveform
”
on page 47
and
Figure 22,
“
WAIT Signal in
Asynchronous Single-Word Read Operation Waveform
”
on page 48
.
From a system perspective, the WAIT signal will be in the asserted state (based on CR.10) when
the device is operating in synchronous non-read array mode (such as Read ID, Read Query, or
Read Status), or if the device is operating in asynchronous mode (CR.15 is set to
“
1
”
). In these
cases, the system software should ignore (mask) the WAIT signal, as it does not convey any useful
information about the validity of what is appearing on the data bus.
Systems may tie several components
’
WAIT signals together.
4.2.5
Data Output Configuration (DOC)
The Data Output Configuration bit (CR.9) determines whether a data word remains valid on the
data bus for one or two clock cycles. The processor
’
s minimum data set-up time and the flash
memory
’
s clock-to-data output delay determine whether one or two clocks are needed.
If the Data Output Configuration is set at one-clock data hold, this corresponds to a one-clock data
cycle; if the Data Output Configuration is set at two-clock data hold, this corresponds to a two-
clock data cycle. This configuration bit
’
s setting depends on the system and CPU characteristics.
Refer to
Figure 8,
“
Data Output Configuration with WAIT Signal Delay
”
on page 18
for
clarification.
A method for determining what this configuration should be set at is shown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:
t
CHQV
(ns) + t
DATA
(ns)
≤
One CLK Period (ns)
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| RD28F6408W30T70 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30) |
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