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RC6100
PRODUCT SPECIFICATION
8
AC Electrical Characteristics
V
CC
= 5V, T
A
= 0 to 70
°
C, unless otherwise specified.
Symbol
V
CS
Parameter
Test Conditions
Maintains lock with
horizontal rate jitter T
<10 ns
CVIN = 1 V
Glitch < 50 ns, Neg polarity,
Voltage relative to blanking;
Test for proper CSYNC
output
Min
150
Typ
Max
600
Units
mV
Composite sync amplitude
HJ
of
p-p
V
IN
Impulse noise immunity
p-p
+ glitch;
0.3
V
f
CLOCK
HFOUT/
D
V
CC
HFPULL
Clock range
VCO power supply rejection rate
HFOUT = 27 MHz
PLL Lock/Hold in Range
code 100
Video in to CSYNC delay
Video in to HRESET delay
H sync to CLAMPgate delay
Duration of HRESET reset
Duration of CLAMPgate
DC=2.5v@PLL filter
Closed loop
12.273
27.0
3.5
MHz
%/V
D
4.5V < V
CCA
< 5.5V
CVIN horizontal frequency
= 15734 Hz nominal
±
500
Hz
Hz
ns
ns
ns
ns
m
s
ns
ns
750
750
750
300
74
t
t
t
t
t
fclk jitter
PD (VCS)
PD (VHS)
PD (HCG)
DHS
fclk = 27 MHz
69
3.0
89
4.5
1
12
DCG
2.5@VCOin code 100
CVin=15.734KHz,
Code 100, fclk=27MHz
fin=15.734+500Hz to
15.625-500Hz
6
Capture Range
200
Hz
PLLFilter
CLDIV
Sink/source current
VOL @ 4mA
VOH
±
150
240
±
350
0.8
m
A
V
V
3.5
Typical Application
Figure 6 shows the RC6100 Horizontal Line Genlock used in
a video signal-processing system. The part provides the
clock that is required to synchronize the various elements of
the system. Note that the clamp gate output of the RC6100 is
applied to the convert input of the TMC1175 ADC.
Figure 6. Application of RC6100 with TMC1175 and TDC3310 in Video Processing System
65-6100-08
ANTI-ALIASING
LFILTER3
VIDEO
INPUT
DSP
SYSTEM
SMOOTHING
RECFILTER3
BUFFER
DRIVER
75
W
8
8
75
W
SYSTEM
SAMPLE
CLOCK
VIDEO
OUTPUT
GENLOCK
RC6100
CONV
CVIN
CLKOUT
ADC
DAC
1
2
Note:
1. Raytheon TMC1175A
2. Raytheon TDC3310
3. Raytheon RC6601