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PRODUCT SPECIFICATION
RC7101
5
Byte writing sequence
The buffer is accessed when the slave address byte is
received. Each byte of data is followed by an acknowledge
bit. The address bit sequence is 1 1 0 1 0 0 1 followed by the
R/W# bit (0). Bits are written with the Most Significant Bit
(MSB) first. The MSB Bit is bit 7 and the LSB is bit 0.
The Byte writing sequence is as shown in the table below.
Data Bytes 0 to 2 Map
Byte
Sequence
1
2
3
4
5
6
7
8
9
10
Byte name
Slave address
Command Code
Byte Count
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Bit sequence
7
1 1
X
X
see table below
see table below
see table below
X
X
X
X
X
X
X
X
6
5
0
X
X
4
1
X
X
3
0
X
X
2
0
X
X
1
1
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
Data Byte 0: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
7
18
6
17
5
14
4
13
3
9
2
8
1
5
0
4
Data Byte 1: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
7
45
6
44
5
41
4
40
3
36
2
35
1
32
0
31
Data Byte 2: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
7
28
6
21
5
4
3
2
1
0
Pin
Name
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
SDRAM15
SDRAM14
SDRAM13
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
SDRAM17
SDRAM16
reserved
reserved
reserved
reserved
reserved
reserved
(ACTIVE/INACTIVE)
(ACTIVE/INACTIVE)
reserved
reserved
reserved
reserved
reserved
reserved