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RC7144
PRODUCT SPECIFICATION
8
P
Writing Data Bytes
Each bit of the 8 data bytes controls a particular device func-
tion except for the “reserved bits”. These must be preserved
by writing a logic 0. Bit 7, the MSB, is written first. See
Table 3 for bit descriptions of Data Bytes 1-4.
Table 5 shows additional frequency selections that are
programmable via the serial data interface.
Table 4 shows the mode select for byte 0, Bit 1and 0.
Table 3. Data Bytes 0–7 Serial Configuration Map
Bit(s)
Data Byte 0
7
6
5
4
3
Affected Pin
Pin No.
Control Function
Bit Control
Default
Pin Name
0
1
-
-
-
-
-
-
-
-
-
-
Spread Mode
FS 2
FS 1
FS 0
Hardware/Software
Frequency Select
FS3
Bit 1
Bit 0
0
0
0
1
1
0
1
0
Center
-
-
-
Hardware
Down
-
-
-
Software
0
0
0
0
0
2
-
-
-
-
-
-
0
1–0
Function (see Table 4)
Normal Operation
Reserved
Spread Spectrum on
All Outputs Tristated
00
Data Byte 1
7
6
5
4
3
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Test Mode
Clock Output Disabled
Reserved
Clock Output Disabled
Clock Output Disabled
-
-
-
-
-
-
0
0
0
1
1
0
1
1
Test Mode
Low
-
Low
Low
Normal
Active
-
Active
Active
40
-
43
44
SDRAM_F
-
CPU1
CPU_F
-
7
-
-
Reserved
Clock Output Disabled
Reserved
Clock Output Disabled
Clock Output Disabled
Clock Output Disabled
Clock Output Disabled
Clock Output Disabled
-
-
0
1
0
1
1
1
1
1
PCI_F
Low
-
Low
Low
Low
Low
Low
Active
-
Active
Active
Active
Active
Active
13
12
11
10
8
PCI5
PCI4
PCI3
PCI2
PCI1
-
-
-
-
Reserved
Reserved
Clock Output Disabled
Clock Output Disabled
Reserved
-
-
-
-
0
0
1
1
0
26
25
-
48 MHz
24MHz
-
Low
Low
-
Active
Active
-