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RC7106
PRODUCT SPECIFICATION
12
PCI Clock Outputs, PCI0:7 (Lump Capacitance Test Load = 30pF)
3V66 Clock Outputs (Lump Capacitance Test Load = 30pF)
CPU/2 Clock Output (Lump Capacitance Test Load = 20pF)
Parameter
t
P
t
H
t
L
t
R
t
F
t
D
t
JC
t
SK
t
O
PCI = 33.3MHz
Min.
Typ.
30
12.0
12.0
0.5
0.5
45
Units
nS
nS
nS
nS
nS
%
pS
pS
nS
Test Condition/Comment
Meas. at rising edge at 1.5V.
Duration of clock cycle above 2.4V.
Duration of clock cycle below 0.4V
0.4V to 2.4V
2.4V to 0.4V
Measured at 1.5V
Measured on rising edge at 1.5V.
Measured on rising edge at 1.5V.
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
Max.
Period
High Time
Low Time
Output Rise Time
Output Fall Time
Duty Cycle
Jitter, Cycle to Cycle
Output Skew
CPU to PCI Clock Offset
2
2
55
500
500
4.0
1.5
Parameter
f
t
R
t
F
t
D
t
jc
t
SK
f
ST
CPU = 133MHz
Min.
Typ.
66.6
0.5
0.5
45
Units
MHz
nS
nS
%
pS
pS
mS
Test Condition/Comment
Max.
Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Jitter, Cycle-to-cycle
Output Skew
Frequency Stabilization
from Power-up
AC Output Impedance
2
2
0.4V to 2.4V
2.4V to 0.4V
Measured at 1.5V
Measured on rising edge at 1.5V
Measured at 1.5V
Assumes full supply voltage reached within 1mS
from power-up.
Average value during switching transition. Used
for determining series termination value.
55
500
250
3
Z
O
20
ohm
Parameter
f
t
R
t
F
t
D
t
jc
t
SK
f
ST
CPU = 133MHz
Min.
Typ.
66.6
0.5
0.5
45
Units
MHz
nS
nS
%
pS
pS
mS
Test Condition/Comment
Max.
Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Jitter, Cycle-to-cycle
Output Skew
Frequency Stabilization
from Power-up
AC Output Impedance
2
2
0.4V to 2.4V
2.4V to 0.4V
Measured at 1.5V
Measured on rising edge at 1.5V
Measured at 1.25V
Assumes full supply voltage reached within 1mS
from power-up.
Average value during switching transition. Used
for determining series termination value.
55
250
175
3
Z
O
20
ohm