- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄225025 > RC28F256P33T85A (NUMONYX) 16M X 16 FLASH 3V PROM, 85 ns, PBGA64 PDF資料下載
參數(shù)資料
| 型號(hào)： | RC28F256P33T85A |
| 廠(chǎng)商： | NUMONYX |
| 元件分類(lèi)： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 85 ns, PBGA64 |
| 封裝： | BGA-64 |
| 文件頁(yè)數(shù)： | 78/96頁(yè) |
| 文件大?。?/td> | 1378K |
| 代理商： | RC28F256P33T85A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)當(dāng)前第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)
Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
8
Order Number: 314749-05
2.0
Functional Overview
This section provides an overview of the features and capabilities of the Numonyx
StrataFlash Embedded Memory (P33) device.
The Kearny Family Flash memory provides density upgrades from 64-Mbit through 512-
Mbit. This family of devices provides high performance at low voltage on a 16-bit data
bus. Individually erasable memory blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the RCR enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal.
A WAIT signal provides an easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. Designed for low-
voltage systems, the Kearny Family Flash memory supports read operations with VCC at
3.0V, and erase and program operations with VPP at 3.0V or 9.0V. BEFP provides the
fastest flash array programming performance with VPP at 9.0V, which increases factory
throughput. With VPP at 3.0V, VCC and VPP can be tied together for a simple, ultra low
power design. In addition to voltage flexibility, a dedicated VPP connection provides
complete data protection when VPP ≤ VPPLK.
The CUI is the interface between the system processor and all internal operations of
the device. An internal WSM automatically executes the algorithms and timings
necessary for block erase and program. A Status Register indicates erase or program
completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The Kearny Family Flash memory protection register allows unique flash device
identification that can be used to increase system security. The individual Block Lock
feature provides zero-latency block locking and unlocking. In addition, the Kearny
Family Flash memory may also pre-define main array space as OTP.
2.1
Virtual Chip Enable Description
The 512 Mbit Kearny Family Flash memory employs a Virtual Chip Enable which
combines two 256-Mbit die with a common chip enable, F1-CE# for QUAD+ packages
Address A24 (QUAD+ package) or A25 (Easy BGA and TSOP package) is then used to
select between the die pair with F1-CE# / CE# asserted, depending upon the package
option used. When chip enable is asserted and QUAD+ A24 (Easy BGA A25) is low
(VIL), The lower parameter die is selected; when chip enable is asserted and QUAD+
additional details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RC28F160C3TC90 | 1M X 16 FLASH 3V PROM, 90 ns, PBGA64 |
| RC28F160C3BD70 | 1M X 16 FLASH 3V PROM, 70 ns, PBGA64 |
| RC4194K | DUAL OUTPUT, ADJUSTABLE MIXED REGULATOR, MBFM9 |
| RM4194K | DUAL OUTPUT, ADJUSTABLE MIXED REGULATOR, MBFM9 |
| RC4194D | DUAL OUTPUT, ADJUSTABLE MIXED REGULATOR, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RC28F256P33T85B | 制造商:Micron Technology Inc 功能描述:256MB, KEARNY EBGA 3.0 - Tape and Reel |
| RC28F256P33TFA | 功能描述:IC FLASH 256MBIT 95NS 64EZBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:Axcell™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤(pán) 其它名稱(chēng):71P71804S200BQ |
| RC28F256P33TFE | 功能描述:IC FLASH 256MBIT 64EZBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:Axcell™ 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤(pán) |
| RC28F320C3 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:3 VOLT ADVANCED+ BOOT BLOCK 8-, 16-, 32-MBIT FLASH MEMORY FAMILY |
| RC28F320C3BA100 | 功能描述:IC FLASH 32MBIT 100NS 64BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類(lèi)型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線(xiàn)串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。