參數(shù)資料
型號(hào)： QLPXA262B1C300
廠商： MARVELL SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA294
封裝： 13 X 13 MM, 1.4MM PITCH, PLASTIC, TPBGA-294
文件頁(yè)數(shù)： 30/44頁(yè)
文件大?。?/td> 1302K
代理商： QLPXA262B1C300
Electrical Specifications
36
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
Table 21. Card Interface (PCMCIA or Compact Flash) AC Specifications
Symbol
Description
MEMCLKs
tcardAS
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE, nPOE, nPIOW, or
nPIOR asserted
2
tcardAH
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE, nPOE, nPIOW, or
nPIOR de-asserted
2
tcardDS
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR asserted
2
tcardDH
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR de-asserted
2
tcardCMD
nPWE, nPOE, nPIOW, or nPIOR command assertion
2
NOTE: These numbers are minimums. They can be much longer based on the programmable card
interface timing registers.
Table 22. Synchronous Memory Interface AC Specifications 1
Symbol
Description
MIN
MAX
Units,
Notes
SDRAM / SMROM / SDRAM-Timing Synchronous Flash (Synchronous)
tsynCLK
SDCLK period
10
20
ns, 2
tsynCMD
nSDCAS, nSDRAS, nWE, nSDCS assert time
1
sdclk
tsynRCD
nSDRAS to nSDCAS assert time
1
sdclk
tsynCAS
nSDCAS to nSDCAS assert time
2
sdclk
tsynSDOS
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
nWE, nOE, SDCKE(1:0), RDnWR output setup time to SDCLK(2:0)
rise
3.8
ns, 3
tsynSDOH
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS,
nWE, nOE, SDCKE(1:0), RDnWR output hold time from
SDCLK(2:0) rise
3.6
ns, 3
tsynSDIS
MD(31:0) read data input setup time from SDCLK(2:0) rise
0.5
ns
tsynDIH
MD(31:0) read data input hold time from SDCLK(2:0) rise
1.5
ns
Fast Flash (Synchronous READS only)
tffCLK
SDCLK period
15
20
ns, 4
tffAS
MA(25:0) setup to nSDCAS (as nADV) asserted
0.5
sdclk
tffCES
nCS setup to nSDCAS (as nADV) asserted
0.5
sdclk
tffADV
nSDCAS (as nADV) pulse width
1
sdclk
tffOS
nSDCAS (as nADV) de-assertion to nOE assertion
3
sdclk
tffCEH
nOE deassertion to nCS de-assertion
4
sdclk
NOTES:
1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.
2. SDCLK for SDRAM, SMROM, and SDRAM-timing Synchronous Flash can be at the slowest, divide-by-2 of
the 99.5 MHz MEMCLK. It can be 99.5 MHz at the fastest.
3. This number represents 1/2 SDCLK period.
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of
the 132.7 MHz MEMCLK at its fastest.
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