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參數(shù)資料
| 型號： | QLPXA262B1C300 |
| 廠商： | MARVELL SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA294 |
| 封裝： | 13 X 13 MM, 1.4MM PITCH, PLASTIC, TPBGA-294 |
| 文件頁數(shù)： | 29/44頁 |
| 文件大?。?/td> | 1302K |
| 代理商： | QLPXA262B1C300 |
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Electrical Specifications
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
35
4.8
Memory Bus and PCMCIA AC Specifications
This section provides the timing information for these types of memory:
SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table 19, “SRAM /
Variable latency I/O (Table 20, “Variable Latency I/O Interface AC Specifications” on
Card interface (PCMCIA or Compact Flash) (Table 21, “Card Interface (PCMCIA or Compact
Synchronous memories (Table 22, “Synchronous Memory Interface AC Specifications 1” on
Table 19. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications
Symbol
Description
MEMCLKs
tromAS
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV) asserted
1
tromAH
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV) de-
asserted
1
tromASW
MA(25:0) setup to nWE asserted
3
tromAHW
MA(25:0) hold after nWE de-asserted
1
tromCES
nCS setup to nWE asserted
2
tromCEH
nCS hold after nWE de-asserted
1
tromDS
MD(31:0), DQM(3:0) write data setup to nWE asserted
1
tromDSWH MD(31:0), DQM(3:0) write data setup to nWE de-asserted
2
tromDH
MD(31:0), DQM(3:0) write data hold after nWE de-asserted
1
tromNWE
nWE high time between beats of write data
2
Table 20. Variable Latency I/O Interface AC Specifications
Symbol
Description
MEMCLKs
tvlioAS
MA(25:0) setubp to nCS asserted
1
tvlioASRW MA(25:0) setup to nOE or nPWE asserted
1
tvlioAH
MA(25:0) hold after nOE or nPWE de-asserted
1
tvlioCES
nCS setup to nOE or nPWE asserted
2
tvlioCEH
nCS hold after nOE or nPWE de-asserted
1
tvlioDSW
MD(31:0), DQM(3:0) write data setup to nPWE asserted
1
tvlioDSWH
MD(31:0), DQM(3:0) write data setup to nPWE de-
asserted
2
tvlioDHW
MD(31:0), DQM(3:0) hold after nPWE de-asserted
1
tvlioDHR
MD(31:0) read data hold after nOE de-asserted
0
tvlioRDYH
RDY hold after nOE, nPWE de-asserted
0
tvlioNPWE nPWE, nOE high time between beats of write or read data
2
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