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參數(shù)資料
| 型號： | QL82SD-PQ208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| 中文描述： | 10高速總線LVDS串行鏈路的帶寬高達(dá)5Gbps的 |
| 文件頁數(shù)： | 46/60頁 |
| 文件大?。?/td> | 3838K |
| 代理商： | QL82SD-PQ208 |
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www.quicklogic.com
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
46
IEEE Standard 1149.1a
The QuickSD device supports IEEE standard 1149.1a. The following public instructions are
supported: BYPASS, EXTEST, and SAMPLE/PRELOAD. Two additional modes RAMWT
and RAMRD can be used to load the RAM.
Figure 55: JTAG Block Diagram
JTAG BSDL Support
BSDL-Boundary Scan Description Language
Machine-readable data for test equipment to generate testing vectors and software
BSDL files available for all device/ package combinations from QuickLogic
Extensive industry support available and ATG (Automatic Test-vector Generation)
Security Fuses
There are two security links, one to disable reading from the array and the other to disable
JTAG.
8-bit Programming
The QuickSD device has 8-bit programming capability. The addition of four extra
programming supplies is used in the reduction of programming time.
TCK
TMS
TRSTB
Logic Cell
Array
I/O Registers
User Defined Data Register
Bypass
Register
Boundary-Scan Register
(Data Register)
Mux
Instruction Register
Mux
Tap Controller
State Machine
(16 States)
Instruction Decode
&
Control Logic
RDI
TDO
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