- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361294 > QL82SD-PQ208 (Electronic Theatre Controls, Inc.) 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps PDF資料下載
參數(shù)資料
| 型號： | QL82SD-PQ208 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| 中文描述： | 10高速總線LVDS串行鏈路的帶寬高達5Gbps的 |
| 文件頁數(shù)： | 42/60頁 |
| 文件大小： | 3838K |
| 代理商： | QL82SD-PQ208 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
www.quicklogic.com
2002 QuickLogic Corporation
QL82SD Device Data Sheet Rev C
Preliminary
42
Figure 51: QuickSD I/O Cell
The bi-directional I/O pin options can be programmed for input, output, or bi-directional
operation. Each bi-directional I/O pin is associated with an I/O cell which features an
input/feedback register, an input buffer, output/feedback register, three-state output buffer,
an output enable register, and two 2-to-1 multiplexers.
For input functions, I/O pins can provide combinatorial
registered data or both options
simultaneously to the logic array. For combinatorial input operation, data is routed from I/O
pins through the input buffer to the array logic. For registered input operation, I/O pins drive
the D input of input cell registers, allowing data to be captured with fast set-up times without
consuming internal logic cell resources.
For output functions, I/O pins can receive combinatorial or registered data from the logic
array. For combinatorial output operation, data is routed from the logic array through a
multiplexer to the I/O pin. For registered output operation, the array logic drives the D input
of the output cell register which in turn drives the I/O pin through a multiplexer. The
multiplexer allows either a combinatorial or a registered signal to be driven to the I/O pin.
The three-state output buffer controls the flow of data from the array logic to the I/O pin and
allows the I/O pin to act as an input and/or output. The buffer's output enable can be
individually controlled by a logic cell array or any pin (through the regular routing resources),
or bank-controlled through one of the global networks.
The signal can also be either combinatorial or registered. This is identical to that of the flow
for the output cell. For combinatorial control operation, data is routed from the logic array
through a multiplexer to the three-state control. For registered control operation, the array
logic drives the D input of the OE cell register which in turn drives the three-state control
through a multiplexer. The multiplexer allows either a combinatorial or a registered signal to
be driven to the three-state control.
For output functions, I/O pins can be individually configured for active HIGH, active LOW,
or open-drain inverting operation. In the active HIGH and active LOW modes, the pins of
all devices are fully 3.3 V compliant.
E
Q
R
D
E
D
R
Q
PAD
E
D
R
Q
+
-
相關PDF資料 |
PDF描述 |
|---|---|
| QL82SD-PS484 | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PT280 | 10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD | QuickSD ESP Family Programmable High-Speed Serial Interface Devices(QuickSD ESP系列可編程高速串行接口器件) |
| QL81SD | QuickSD ESP Family Programmable High-Speed Serial Interface Devices(QuickSD ESP系列可編程高速串行接口器件) |
| QL84SD | QuickSD ESP Family Programmable High-Speed Serial Interface Devices(QuickSD ESP系列可編程高速串行接口器件) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| QL82SD-PS484 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PT280 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL8325 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8325-8PS484C-5192 | 制造商:QuickLogic Corporation 功能描述: |
| QL8325-8PS484C-5995 | 制造商:QuickLogic Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。